Lines Matching full:gpio
10 #include <linux/gpio/aspeed.h>
11 #include <linux/gpio/driver.h>
26 * These two headers aren't meant to be used by GPIO drivers. We need
31 #include <linux/gpio/consumer.h>
76 * represents disabled debouncing for the GPIO. Any other value for an element
110 * line even when the GPIO is configured as an output. Since
224 void (*reg_bit_set)(struct aspeed_gpio *gpio, unsigned int offset,
226 bool (*reg_bit_get)(struct aspeed_gpio *gpio, unsigned int offset,
228 int (*reg_bank_get)(struct aspeed_gpio *gpio, unsigned int offset,
230 void (*privilege_ctrl)(struct aspeed_gpio *gpio, unsigned int offset, int owner);
231 void (*privilege_init)(struct aspeed_gpio *gpio);
232 bool (*copro_request)(struct aspeed_gpio *gpio, unsigned int offset);
233 void (*copro_release)(struct aspeed_gpio *gpio, unsigned int offset);
256 static void __iomem *aspeed_gpio_g4_bank_reg(struct aspeed_gpio *gpio,
262 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
264 return gpio->base + bank->rdata_reg;
266 return gpio->base + bank->val_regs + GPIO_VAL_DIR;
268 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
270 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
272 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
274 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
276 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
278 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
280 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
282 return gpio->base + bank->tolerance_regs;
284 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
286 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
342 struct aspeed_gpio *gpio, unsigned int offset)
344 const struct aspeed_bank_props *props = gpio->config->props;
355 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
357 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
359 if (offset >= gpio->chip.ngpio)
365 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
367 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
375 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
377 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
382 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc)
384 if (gpio->config->llops->privilege_ctrl)
385 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc);
388 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
391 if (gpio->config->llops->copro_request)
392 return gpio->config->llops->copro_request(gpio, offset);
397 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
400 if (gpio->config->llops->copro_release)
401 gpio->config->llops->copro_release(gpio, offset);
404 static bool aspeed_gpio_support_copro(struct aspeed_gpio *gpio)
406 return gpio->config->llops->copro_request && gpio->config->llops->copro_release &&
407 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init;
412 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
414 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val);
420 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
422 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val);
424 gpio->config->llops->reg_bit_get(gpio, offset, reg_val);
429 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
432 guard(raw_spinlock_irqsave)(&gpio->lock);
434 copro = aspeed_gpio_copro_request(gpio, offset);
439 aspeed_gpio_copro_release(gpio, offset);
446 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
449 if (!have_input(gpio, offset))
452 guard(raw_spinlock_irqsave)(&gpio->lock);
454 copro = aspeed_gpio_copro_request(gpio, offset);
455 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0);
457 aspeed_gpio_copro_release(gpio, offset);
465 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
468 if (!have_output(gpio, offset))
471 guard(raw_spinlock_irqsave)(&gpio->lock);
473 copro = aspeed_gpio_copro_request(gpio, offset);
475 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1);
478 aspeed_gpio_copro_release(gpio, offset);
485 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
488 if (!have_input(gpio, offset))
491 if (!have_output(gpio, offset))
494 guard(raw_spinlock_irqsave)(&gpio->lock);
496 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir);
502 struct aspeed_gpio **gpio,
515 *gpio = internal;
522 struct aspeed_gpio *gpio;
526 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset);
530 guard(raw_spinlock_irqsave)(&gpio->lock);
532 copro = aspeed_gpio_copro_request(gpio, offset);
534 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1);
537 aspeed_gpio_copro_release(gpio, offset);
542 struct aspeed_gpio *gpio;
546 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset);
552 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d));
554 guard(raw_spinlock_irqsave)(&gpio->lock);
556 copro = aspeed_gpio_copro_request(gpio, offset);
558 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set);
561 aspeed_gpio_copro_release(gpio, offset);
565 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d));
584 struct aspeed_gpio *gpio;
588 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset);
613 scoped_guard(raw_spinlock_irqsave, &gpio->lock) {
614 copro = aspeed_gpio_copro_request(gpio, offset);
616 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0,
618 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1,
620 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2,
624 aspeed_gpio_copro_release(gpio, offset);
638 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
642 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
644 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status);
657 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
658 const struct aspeed_bank_props *props = gpio->config->props;
664 /* Pretty crummy approach, but similar to GPIO core */
668 if (i >= gpio->chip.ngpio)
681 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
684 guard(raw_spinlock_irqsave)(&gpio->lock);
686 copro = aspeed_gpio_copro_request(gpio, offset);
688 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable);
691 aspeed_gpio_copro_release(gpio, offset);
709 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
716 rate = clk_get_rate(gpio->clk);
732 /* Call under gpio->lock */
733 static int register_allocated_timer(struct aspeed_gpio *gpio,
736 if (WARN(gpio->offset_timer[offset] != 0,
738 offset, gpio->offset_timer[offset]))
741 if (WARN(gpio->timer_users[timer] == UINT_MAX,
745 gpio->offset_timer[offset] = timer;
746 gpio->timer_users[timer]++;
751 /* Call under gpio->lock */
752 static int unregister_allocated_timer(struct aspeed_gpio *gpio,
755 if (WARN(gpio->offset_timer[offset] == 0,
759 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
761 gpio->offset_timer[offset]))
764 gpio->timer_users[gpio->offset_timer[offset]]--;
765 gpio->offset_timer[offset] = 0;
770 /* Call under gpio->lock */
771 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
774 return gpio->offset_timer[offset] > 0;
777 /* Call under gpio->lock */
778 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
784 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1)));
785 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0)));
791 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
796 if (!gpio->clk)
799 rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
802 usecs, clk_get_rate(gpio->clk), rc);
806 guard(raw_spinlock_irqsave)(&gpio->lock);
808 if (timer_allocation_registered(gpio, offset)) {
809 rc = unregister_allocated_timer(gpio, offset);
815 for (i = 1; i < gpio->config->debounce_timers_num; i++) {
818 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]);
823 if (i == gpio->config->debounce_timers_num) {
830 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
831 if (gpio->timer_users[j] == 0)
835 if (j == ARRAY_SIZE(gpio->timer_users)) {
848 configure_timer(gpio, offset, 0);
854 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]);
860 register_allocated_timer(gpio, offset, i);
861 configure_timer(gpio, offset, i);
868 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
871 guard(raw_spinlock_irqsave)(&gpio->lock);
873 rc = unregister_allocated_timer(gpio, offset);
875 configure_timer(gpio, offset, 0);
883 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
885 if (!have_debounce(gpio, offset))
918 * the coprocessor for shared GPIO banks
932 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
935 * @desc: The GPIO to be marked
936 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
937 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
938 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
944 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
948 if (!aspeed_gpio_support_copro(gpio))
951 if (!gpio->cf_copro_bankmap)
952 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
953 if (!gpio->cf_copro_bankmap)
955 if (offset < 0 || offset > gpio->chip.ngpio)
959 guard(raw_spinlock_irqsave)(&gpio->lock);
962 if (gpio->cf_copro_bankmap[bindex] == 0xff)
965 gpio->cf_copro_bankmap[bindex]++;
968 if (gpio->cf_copro_bankmap[bindex] == 1)
969 aspeed_gpio_change_cmd_source(gpio, offset,
983 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
984 * @desc: The GPIO to be marked
989 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
992 if (!aspeed_gpio_support_copro(gpio))
995 if (!gpio->cf_copro_bankmap)
998 if (offset < 0 || offset > gpio->chip.ngpio)
1002 guard(raw_spinlock_irqsave)(&gpio->lock);
1005 if (gpio->cf_copro_bankmap[bindex] == 0)
1008 gpio->cf_copro_bankmap[bindex]--;
1011 if (gpio->cf_copro_bankmap[bindex] == 0)
1012 aspeed_gpio_change_cmd_source(gpio, offset,
1021 struct aspeed_gpio *gpio;
1024 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset);
1028 seq_puts(p, dev_name(gpio->dev));
1041 static void aspeed_g4_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset,
1045 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);
1049 temp = gpio->dcache[GPIO_BANK(offset)];
1059 gpio->dcache[GPIO_BANK(offset)] = temp;
1063 static bool aspeed_g4_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset,
1067 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);
1072 static int aspeed_g4_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset,
1076 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);
1084 static void aspeed_g4_privilege_ctrl(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc)
1091 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc1, !!(cmdsrc & BIT(1)));
1093 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc0, !!(cmdsrc & BIT(0)));
1096 static void aspeed_g4_privilege_init(struct aspeed_gpio *gpio)
1101 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) {
1102 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 0, GPIO_CMDSRC_ARM);
1103 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 8, GPIO_CMDSRC_ARM);
1104 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 16, GPIO_CMDSRC_ARM);
1105 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 24, GPIO_CMDSRC_ARM);
1109 static bool aspeed_g4_copro_request(struct aspeed_gpio *gpio, unsigned int offset)
1111 if (!copro_ops || !gpio->cf_copro_bankmap)
1113 if (!gpio->cf_copro_bankmap[offset >> 3])
1122 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_ARM);
1125 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata);
1130 static void aspeed_g4_copro_release(struct aspeed_gpio *gpio, unsigned int offset)
1132 if (!copro_ops || !gpio->cf_copro_bankmap)
1134 if (!gpio->cf_copro_bankmap[offset >> 3])
1140 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_COLDFIRE);
1156 static void aspeed_g7_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset,
1160 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset);
1169 static bool aspeed_g7_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset,
1175 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset);
1185 static int aspeed_g7_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset,
1191 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5);
1218 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1223 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1236 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1242 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1277 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */
1285 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH)
1299 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1300 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1301 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1302 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, },
1311 struct aspeed_gpio *gpio;
1315 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
1316 if (!gpio)
1319 gpio->base = devm_platform_ioremap_resource(pdev, 0);
1320 if (IS_ERR(gpio->base))
1321 return PTR_ERR(gpio->base);
1323 gpio->dev = &pdev->dev;
1325 raw_spin_lock_init(&gpio->lock);
1331 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1332 if (IS_ERR(gpio->clk)) {
1335 gpio->clk = NULL;
1338 gpio->config = gpio_id->data;
1340 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get ||
1341 !gpio->config->llops->reg_bank_get)
1344 gpio->chip.parent = &pdev->dev;
1346 gpio->chip.ngpio = (u16) ngpio;
1348 gpio->chip.ngpio = gpio->config->nr_gpios;
1349 gpio->chip.direction_input = aspeed_gpio_dir_in;
1350 gpio->chip.direction_output = aspeed_gpio_dir_out;
1351 gpio->chip.get_direction = aspeed_gpio_get_direction;
1352 gpio->chip.request = aspeed_gpio_request;
1353 gpio->chip.free = aspeed_gpio_free;
1354 gpio->chip.get = aspeed_gpio_get;
1355 gpio->chip.set_rv = aspeed_gpio_set;
1356 gpio->chip.set_config = aspeed_gpio_set_config;
1357 gpio->chip.label = dev_name(&pdev->dev);
1358 gpio->chip.base = -1;
1360 if (gpio->config->require_dcache) {
1362 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
1363 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL);
1364 if (!gpio->dcache)
1370 gpio->dcache[i] =
1371 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata);
1374 if (gpio->config->llops->privilege_init)
1375 gpio->config->llops->privilege_init(gpio);
1381 gpio->irq = irq;
1382 girq = &gpio->chip.irq;
1390 girq->parents[0] = gpio->irq;
1395 gpio->offset_timer =
1396 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
1397 if (!gpio->offset_timer)
1400 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
1417 MODULE_DESCRIPTION("Aspeed GPIO Driver");