Lines Matching +full:reg +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-or-later
106 const enum aspeed_sgpio_reg reg) in bank_reg() argument
108 switch (reg) { in bank_reg()
110 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
112 return gpio->base + bank->rdata_reg; in bank_reg()
114 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
116 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
118 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
120 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
122 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
124 return gpio->base + bank->tolerance_regs; in bank_reg()
135 static const struct aspeed_sgpio_bank *to_bank(unsigned int offset) in to_bank() argument
139 bank = GPIO_BANK(offset); in to_bank()
164 static bool aspeed_sgpio_is_input(unsigned int offset) in aspeed_sgpio_is_input() argument
166 return !(offset % 2); in aspeed_sgpio_is_input()
169 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset) in aspeed_sgpio_get() argument
172 const struct aspeed_sgpio_bank *bank = to_bank(offset); in aspeed_sgpio_get()
174 enum aspeed_sgpio_reg reg; in aspeed_sgpio_get() local
177 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_get()
179 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; in aspeed_sgpio_get()
180 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
182 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_get()
187 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val) in sgpio_set_value() argument
190 const struct aspeed_sgpio_bank *bank = to_bank(offset); in sgpio_set_value()
192 u32 reg = 0; in sgpio_set_value() local
194 if (aspeed_sgpio_is_input(offset)) in sgpio_set_value()
195 return -EINVAL; in sgpio_set_value()
202 reg = ioread32(addr_r); in sgpio_set_value()
205 reg |= GPIO_BIT(offset); in sgpio_set_value()
207 reg &= ~GPIO_BIT(offset); in sgpio_set_value()
209 iowrite32(reg, addr_w); in sgpio_set_value()
214 static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val) in aspeed_sgpio_set() argument
219 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_set()
221 sgpio_set_value(gc, offset, val); in aspeed_sgpio_set()
223 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_set()
226 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset) in aspeed_sgpio_dir_in() argument
228 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL; in aspeed_sgpio_dir_in()
231 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val) in aspeed_sgpio_dir_out() argument
238 * error-out in sgpio_set_value if this isn't an output GPIO */ in aspeed_sgpio_dir_out()
240 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_dir_out()
241 rc = sgpio_set_value(gc, offset, val); in aspeed_sgpio_dir_out()
242 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_dir_out()
247 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset) in aspeed_sgpio_get_direction() argument
249 return !!aspeed_sgpio_is_input(offset); in aspeed_sgpio_get_direction()
255 u32 *bit, int *offset) in irqd_to_aspeed_sgpio_data() argument
259 *offset = irqd_to_hwirq(d); in irqd_to_aspeed_sgpio_data()
264 *bank = to_bank(*offset); in irqd_to_aspeed_sgpio_data()
265 *bit = GPIO_BIT(*offset); in irqd_to_aspeed_sgpio_data()
274 int offset; in aspeed_sgpio_irq_ack() local
277 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_ack()
281 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_irq_ack()
285 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_irq_ack()
293 u32 reg, bit; in aspeed_sgpio_irq_set_mask() local
295 int offset; in aspeed_sgpio_irq_set_mask() local
297 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_set_mask()
302 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_sgpio_irq_set_mask()
304 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_irq_set_mask()
306 reg = ioread32(addr); in aspeed_sgpio_irq_set_mask()
308 reg |= bit; in aspeed_sgpio_irq_set_mask()
310 reg &= ~bit; in aspeed_sgpio_irq_set_mask()
312 iowrite32(reg, addr); in aspeed_sgpio_irq_set_mask()
314 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_irq_set_mask()
318 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_sgpio_irq_set_mask()
338 u32 bit, reg; in aspeed_sgpio_set_type() local
344 int offset; in aspeed_sgpio_set_type() local
346 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_set_type()
366 return -EINVAL; in aspeed_sgpio_set_type()
369 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_set_type()
372 reg = ioread32(addr); in aspeed_sgpio_set_type()
373 reg = (reg & ~bit) | type0; in aspeed_sgpio_set_type()
374 iowrite32(reg, addr); in aspeed_sgpio_set_type()
377 reg = ioread32(addr); in aspeed_sgpio_set_type()
378 reg = (reg & ~bit) | type1; in aspeed_sgpio_set_type()
379 iowrite32(reg, addr); in aspeed_sgpio_set_type()
382 reg = ioread32(addr); in aspeed_sgpio_set_type()
383 reg = (reg & ~bit) | type2; in aspeed_sgpio_set_type()
384 iowrite32(reg, addr); in aspeed_sgpio_set_type()
386 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_set_type()
399 unsigned long reg; in aspeed_sgpio_irq_handler() local
406 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_sgpio_irq_handler()
408 for_each_set_bit(p, ®, 32) in aspeed_sgpio_irq_handler()
409 generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); in aspeed_sgpio_irq_handler()
420 int offset; in aspeed_sgpio_irq_print_chip() local
422 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_print_chip()
423 seq_printf(p, dev_name(gpio->dev)); in aspeed_sgpio_irq_print_chip()
447 gpio->irq = rc; in aspeed_sgpio_setup_irqs()
458 irq = &gpio->chip.irq; in aspeed_sgpio_setup_irqs()
460 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask; in aspeed_sgpio_setup_irqs()
461 irq->handler = handle_bad_irq; in aspeed_sgpio_setup_irqs()
462 irq->default_type = IRQ_TYPE_NONE; in aspeed_sgpio_setup_irqs()
463 irq->parent_handler = aspeed_sgpio_irq_handler; in aspeed_sgpio_setup_irqs()
464 irq->parent_handler_data = gpio; in aspeed_sgpio_setup_irqs()
465 irq->parents = &gpio->irq; in aspeed_sgpio_setup_irqs()
466 irq->num_parents = 1; in aspeed_sgpio_setup_irqs()
471 /* set falling or level-low irq */ in aspeed_sgpio_setup_irqs()
487 unsigned int offset, bool enable) in aspeed_sgpio_reset_tolerance() argument
491 void __iomem *reg; in aspeed_sgpio_reset_tolerance() local
494 reg = bank_reg(gpio, to_bank(offset), reg_tolerance); in aspeed_sgpio_reset_tolerance()
496 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_reset_tolerance()
498 val = readl(reg); in aspeed_sgpio_reset_tolerance()
501 val |= GPIO_BIT(offset); in aspeed_sgpio_reset_tolerance()
503 val &= ~GPIO_BIT(offset); in aspeed_sgpio_reset_tolerance()
505 writel(val, reg); in aspeed_sgpio_reset_tolerance()
507 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_reset_tolerance()
512 static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset, in aspeed_sgpio_set_config() argument
519 return aspeed_sgpio_reset_tolerance(chip, offset, arg); in aspeed_sgpio_set_config()
521 return -ENOTSUPP; in aspeed_sgpio_set_config()
529 { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
530 { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
531 { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
545 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_sgpio_probe()
547 return -ENOMEM; in aspeed_sgpio_probe()
549 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_sgpio_probe()
550 if (IS_ERR(gpio->base)) in aspeed_sgpio_probe()
551 return PTR_ERR(gpio->base); in aspeed_sgpio_probe()
553 gpio->dev = &pdev->dev; in aspeed_sgpio_probe()
555 pdata = device_get_match_data(&pdev->dev); in aspeed_sgpio_probe()
557 return -EINVAL; in aspeed_sgpio_probe()
559 pin_mask = pdata->pin_mask; in aspeed_sgpio_probe()
561 rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios); in aspeed_sgpio_probe()
563 dev_err(&pdev->dev, "Could not read ngpios property\n"); in aspeed_sgpio_probe()
564 return -EINVAL; in aspeed_sgpio_probe()
566 dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n", in aspeed_sgpio_probe()
568 return -EINVAL; in aspeed_sgpio_probe()
571 rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq); in aspeed_sgpio_probe()
573 dev_err(&pdev->dev, "Could not read bus-frequency property\n"); in aspeed_sgpio_probe()
574 return -EINVAL; in aspeed_sgpio_probe()
577 gpio->pclk = devm_clk_get(&pdev->dev, NULL); in aspeed_sgpio_probe()
578 if (IS_ERR(gpio->pclk)) { in aspeed_sgpio_probe()
579 dev_err(&pdev->dev, "devm_clk_get failed\n"); in aspeed_sgpio_probe()
580 return PTR_ERR(gpio->pclk); in aspeed_sgpio_probe()
583 apb_freq = clk_get_rate(gpio->pclk); in aspeed_sgpio_probe()
592 * GPIO254[31:16] = PCLK / (frequency * 2) - 1 in aspeed_sgpio_probe()
595 return -EINVAL; in aspeed_sgpio_probe()
597 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1; in aspeed_sgpio_probe()
599 if (sgpio_clk_div > (1 << 16) - 1) in aspeed_sgpio_probe()
600 return -EINVAL; in aspeed_sgpio_probe()
604 ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL); in aspeed_sgpio_probe()
606 raw_spin_lock_init(&gpio->lock); in aspeed_sgpio_probe()
608 gpio->chip.parent = &pdev->dev; in aspeed_sgpio_probe()
609 gpio->chip.ngpio = nr_gpios * 2; in aspeed_sgpio_probe()
610 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask; in aspeed_sgpio_probe()
611 gpio->chip.direction_input = aspeed_sgpio_dir_in; in aspeed_sgpio_probe()
612 gpio->chip.direction_output = aspeed_sgpio_dir_out; in aspeed_sgpio_probe()
613 gpio->chip.get_direction = aspeed_sgpio_get_direction; in aspeed_sgpio_probe()
614 gpio->chip.request = NULL; in aspeed_sgpio_probe()
615 gpio->chip.free = NULL; in aspeed_sgpio_probe()
616 gpio->chip.get = aspeed_sgpio_get; in aspeed_sgpio_probe()
617 gpio->chip.set = aspeed_sgpio_set; in aspeed_sgpio_probe()
618 gpio->chip.set_config = aspeed_sgpio_set_config; in aspeed_sgpio_probe()
619 gpio->chip.label = dev_name(&pdev->dev); in aspeed_sgpio_probe()
620 gpio->chip.base = -1; in aspeed_sgpio_probe()
624 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_sgpio_probe()