31 #define SCU_COPRO_CTRL			0x100
32 #define   SCU_COPRO_RESET			0x00000002
33 #define   SCU_COPRO_CLK_EN			0x00000001
36 #define SCU_2500_COPRO_SEG0		0x104
37 #define SCU_2500_COPRO_SEG1		0x108
38 #define SCU_2500_COPRO_SEG2		0x10c
39 #define SCU_2500_COPRO_SEG3		0x110
40 #define SCU_2500_COPRO_SEG4		0x114
41 #define SCU_2500_COPRO_SEG5		0x118
42 #define SCU_2500_COPRO_SEG6		0x11c
43 #define SCU_2500_COPRO_SEG7		0x120
44 #define SCU_2500_COPRO_SEG8		0x124
45 #define   SCU_2500_COPRO_SEG_SWAP		0x00000001
46 #define SCU_2500_COPRO_CACHE_CTL	0x128
47 #define   SCU_2500_COPRO_CACHE_EN		0x00000001
48 #define   SCU_2500_COPRO_SEG0_CACHE_EN		0x00000002
49 #define   SCU_2500_COPRO_SEG1_CACHE_EN		0x00000004
50 #define   SCU_2500_COPRO_SEG2_CACHE_EN		0x00000008
51 #define   SCU_2500_COPRO_SEG3_CACHE_EN		0x00000010
52 #define   SCU_2500_COPRO_SEG4_CACHE_EN		0x00000020
53 #define   SCU_2500_COPRO_SEG5_CACHE_EN		0x00000040
54 #define   SCU_2500_COPRO_SEG6_CACHE_EN		0x00000080
55 #define   SCU_2500_COPRO_SEG7_CACHE_EN		0x00000100
56 #define   SCU_2500_COPRO_SEG8_CACHE_EN		0x00000200
58 #define SCU_2400_COPRO_SEG0		0x104
59 #define SCU_2400_COPRO_SEG2		0x108
60 #define SCU_2400_COPRO_SEG4		0x10c
61 #define SCU_2400_COPRO_SEG6		0x110
62 #define SCU_2400_COPRO_SEG8		0x114
63 #define   SCU_2400_COPRO_SEG_SWAP		0x80000000
64 #define SCU_2400_COPRO_CACHE_CTL	0x118
65 #define   SCU_2400_COPRO_CACHE_EN		0x00000001
66 #define   SCU_2400_COPRO_SEG0_CACHE_EN		0x00000002
67 #define   SCU_2400_COPRO_SEG2_CACHE_EN		0x00000004
68 #define   SCU_2400_COPRO_SEG4_CACHE_EN		0x00000008
69 #define   SCU_2400_COPRO_SEG6_CACHE_EN		0x00000010
70 #define   SCU_2400_COPRO_SEG8_CACHE_EN		0x00000020
73 #define CVIC_EN_REG			0x10
74 #define CVIC_TRIG_REG			0x18
80 #define SYSREG_BASE			0x1e600000
83 #define SRAM_SIZE			0x1000
85 #define LAST_ADDR_INVALID		0x1
142 	top = msg->bits & 0x3;  in msg_push_crc()
145 	crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);  in msg_push_crc()
163 	return master->last_addr == (((id & 0x3) << 21) | (addr & ~0x3));  in check_same_address()
179 	if (((last_addr >> 21) & 0x3) != id)  in check_relative_address()
202 		master->last_addr = ((id & 0x3) << 21) | (addr & ~0x3);  in last_address_update()
218 	cmd->bits = 0;  in build_ar_command()
219 	cmd->msg = 0;  in build_ar_command()
251 	 *	size	addr:1	addr:0	ds  in build_ar_command()
252 	 *	1	x	x	0  in build_ar_command()
253 	 *	2	x	0	1  in build_ar_command()
254 	 *	4	0	1	1  in build_ar_command()
257 	ds = size > 1 ? 1 : 0;  in build_ar_command()
264 	msg_push_bits(cmd, write ? 0 : 1, 1);  in build_ar_command()
267 	for (i = 0; write && i < size; i++)  in build_ar_command()
276 	cmd->bits = 0;  in build_dpoll_command()
277 	cmd->msg = 0;  in build_dpoll_command()
287 	cmd->bits = 0;  in build_epoll_command()
288 	cmd->msg = 0;  in build_epoll_command()
298 	cmd->bits = 0;  in build_term_command()
299 	cmd->msg = 0;  in build_term_command()
319 		iowrite32(0x2, master->cvic + CVIC_TRIG_REG);  in do_copro_command()
323 		if (timeout-- == 0) {  in do_copro_command()
329 	} while(stat < STAT_COMPLETE || stat == 0xff);  in do_copro_command()
332 		return 0;  in do_copro_command()
355 	return 0;  in clock_zeros()
367 	iowrite32be((cmd->msg & 0xffffffff), master->sram + CMD_DATA + 4);  in send_request()
380 	uint8_t rtag = ioread8(master->sram + STAT_RTAG) & 0xf;  in read_copro_response()
381 	uint8_t rcrc = ioread8(master->sram + STAT_RCRC) & 0xf;  in read_copro_response()
382 	uint32_t rdata = 0;  in read_copro_response()
389 	crc = crc4(0, 1, 1);  in read_copro_response()
399 	trace_fsi_master_acf_copro_response(master, rtag, rcrc, rdata, crc == 0);  in read_copro_response()
403 		 * Check if it's all 1's or all 0's, that probably means  in read_copro_response()
406 		if ((rtag == 0xf && rcrc == 0xf) || (rtag == 0 && rcrc == 0))  in read_copro_response()
411 	return 0;  in read_copro_response()
422 	rc = send_request(master, &cmd, 0);  in send_term()
428 	rc = read_copro_response(master, 0, NULL, &tag);  in send_term()
429 	if (rc < 0) {  in send_term()
437 	return 0;  in send_term()
454 	for (i = 0; i < 512; i++) {  in dump_ucode_trace()
456 		if ((i % 16) == 0)  in dump_ucode_trace()
470 	int busy_count = 0, rc;  in handle_response()
471 	int crc_err_retries = 0;  in handle_response()
564 	if (busy_count > 0) {  in handle_response()
574 	int rc = -EAGAIN, retries = 0;  in fsi_master_acf_xfer()
605 	if (link != 0)  in fsi_master_acf_read()
612 	last_address_update(master, id, rc == 0, addr);  in fsi_master_acf_read()
614 		dev_dbg(master->dev, "read id %d addr 0x%08x err: %d\n",  in fsi_master_acf_read()
629 	if (link != 0)  in fsi_master_acf_write()
636 	rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);  in fsi_master_acf_write()
637 	last_address_update(master, id, rc == 0, addr);  in fsi_master_acf_write()
639 		dev_dbg(master->dev, "write id %d addr 0x%08x err: %d\n",  in fsi_master_acf_write()
653 	if (link != 0)  in fsi_master_acf_term()
659 	rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);  in fsi_master_acf_term()
660 	last_address_update(master, id, false, 0);  in fsi_master_acf_term()
671 	if (link != 0)  in fsi_master_acf_break()
681 	last_address_update(master, 0, false, 0);  in fsi_master_acf_break()
694 	regmap_write(master->scu, SCU_COPRO_CTRL, 0);  in reset_cf()
721 	/* Setup segment 0 to our memory region */  in setup_ast2500_cf_maps()
728 	regmap_write(master->scu, SCU_2500_COPRO_SEG3, SYSREG_BASE | 0x100000 |  in setup_ast2500_cf_maps()
733 	regmap_write(master->scu, SCU_2500_COPRO_SEG7, SYSREG_BASE | 0x100000);  in setup_ast2500_cf_maps()
742 	/* Setup segment 0 to our memory region */  in setup_ast2400_cf_maps()
819 	return 0;  in setup_gpios_for_copro()
832 	uint16_t sig = 0, wanted_sig;  in load_copro_firmware()
834 	size_t size = 0;  in load_copro_firmware()
891 		 fw_vers, fw_api >> 8, fw_api & 0xff,  in check_firmware_image()
899 	return 0;  in check_firmware_image()
911 	for (timeout = 0; timeout < 10; timeout++) {  in copro_enable_sw_irq()
912 		iowrite32(0x2, master->cvic + CVIC_EN_REG);  in copro_enable_sw_irq()
922 	return 0;  in copro_enable_sw_irq()
937 	memset_io(master->sram, 0, SRAM_SIZE);  in fsi_master_acf_setup()
969 	for (timeout = 0; timeout < 10; timeout++) {  in fsi_master_acf_setup()
991 	return 0;  in fsi_master_acf_setup()
1019 	iowrite32(0, master->sram + CF_STARTED);  in fsi_master_acf_terminate()
1035 	gpiod_direction_output(master->gpio_mux, 0);  in fsi_master_acf_setup_external()
1036 	gpiod_direction_output(master->gpio_trans, 0);  in fsi_master_acf_setup_external()
1048 	if (link != 0)  in fsi_master_acf_link_enable()
1053 		gpiod_set_value(master->gpio_enable, enable ? 1 : 0);  in fsi_master_acf_link_enable()
1054 		rc = 0;  in fsi_master_acf_link_enable()
1066 	if (link != 0)  in fsi_master_acf_link_config()
1078 	return 0;  in fsi_master_acf_link_config()
1087 			master->external_mode ? 1 : 0);  in external_mode_show()
1098 	err = kstrtoul(buf, 0, &val);  in external_mode_store()
1151 	if (ioread32(master->sram + CF_STARTED) == 0) {  in fsi_master_acf_gpio_request()
1152 		unsigned int reg = 0;  in fsi_master_acf_gpio_request()
1156 			return 0;  in fsi_master_acf_gpio_request()
1161 		iowrite32(0x2, master->cvic + CVIC_TRIG_REG);  in fsi_master_acf_gpio_request()
1163 	for (timeout = 0; timeout < 10000; timeout++) {  in fsi_master_acf_gpio_request()
1174 	return 0;  in fsi_master_acf_gpio_request()
1182 	iowrite8(0, master->sram + ARB_REG);  in fsi_master_acf_gpio_release()
1186 		iowrite32(0x2, master->cvic + CVIC_TRIG_REG);  in fsi_master_acf_gpio_release()
1188 	return 0;  in fsi_master_acf_gpio_release()
1246 	gpio = devm_gpiod_get(&pdev->dev, "clock", 0);  in fsi_master_acf_probe()
1254 	gpio = devm_gpiod_get(&pdev->dev, "data", 0);  in fsi_master_acf_probe()
1263 	gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);  in fsi_master_acf_probe()
1271 	gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);  in fsi_master_acf_probe()
1279 	gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);  in fsi_master_acf_probe()
1288 	np = of_parse_phandle(mnode, "memory-region", 0);  in fsi_master_acf_probe()
1294 	rc = of_address_to_resource(np, 0, &res);  in fsi_master_acf_probe()
1303 	cf_mem_align = master->is_ast2500 ? 0x00100000 : 0x00200000;  in fsi_master_acf_probe()
1319 		np = of_parse_phandle(mnode, "aspeed,cvic", 0);  in fsi_master_acf_probe()
1325 		master->cvic = devm_of_iomap(&pdev->dev, np, 0, NULL);  in fsi_master_acf_probe()
1342 	master->sram_pool = of_gen_pool_get(dev_of_node(&pdev->dev), "aspeed,sram", 0);  in fsi_master_acf_probe()
1350 	gpdf.offset = 0;  in fsi_master_acf_probe()
1397 		return 0;  in fsi_master_acf_probe()