Lines Matching +full:fpga +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
12 #include <linux/fpga/fpga-bridge.h>
13 #include <linux/fpga/fpga-mgr.h>
14 #include <linux/fpga/fpga-region.h>
53 struct mgr_stats *stats = mgr->priv; in op_write()
55 stats->write_count++; in op_write()
61 * Fake FPGA manager that implements only the write op to count the number
72 struct bridge_stats *stats = bridge->priv; in op_enable_set()
74 if (!stats->enable && enable) in op_enable_set()
75 stats->cycles_count++; in op_enable_set()
77 stats->enable = enable; in op_enable_set()
83 * Fake FPGA bridge that implements only enable_set op to count the number
92 struct fpga_bridge *bridge = region->priv; in fake_region_get_bridges()
94 return fpga_bridge_get_to_list(bridge->dev.parent, region->info, ®ion->bridge_list); in fake_region_get_bridges()
99 return dev->parent == data; in fake_region_match()
104 struct test_ctx *ctx = test->priv; in fpga_region_test_class_find()
107 region = fpga_region_class_find(NULL, ctx->region_dev, fake_region_match); in fpga_region_test_class_find()
108 KUNIT_EXPECT_PTR_EQ(test, region, ctx->region); in fpga_region_test_class_find()
110 put_device(®ion->dev); in fpga_region_test_class_find()
114 * FPGA Region programming test. The Region must call get_bridges() to get
119 struct test_ctx *ctx = test->priv; in fpga_region_test_program_fpga()
124 img_info = fpga_image_info_alloc(ctx->mgr_dev); in fpga_region_test_program_fpga()
130 img_info->buf = img_buf; in fpga_region_test_program_fpga()
131 img_info->count = sizeof(img_buf); in fpga_region_test_program_fpga()
133 ctx->region->info = img_info; in fpga_region_test_program_fpga()
134 ret = fpga_region_program_fpga(ctx->region); in fpga_region_test_program_fpga()
137 KUNIT_EXPECT_EQ(test, 1, ctx->mgr_stats.write_count); in fpga_region_test_program_fpga()
138 KUNIT_EXPECT_EQ(test, 1, ctx->bridge_stats.cycles_count); in fpga_region_test_program_fpga()
140 fpga_bridges_put(&ctx->region->bridge_list); in fpga_region_test_program_fpga()
142 ret = fpga_region_program_fpga(ctx->region); in fpga_region_test_program_fpga()
145 KUNIT_EXPECT_EQ(test, 2, ctx->mgr_stats.write_count); in fpga_region_test_program_fpga()
146 KUNIT_EXPECT_EQ(test, 2, ctx->bridge_stats.cycles_count); in fpga_region_test_program_fpga()
148 fpga_bridges_put(&ctx->region->bridge_list); in fpga_region_test_program_fpga()
166 ctx->mgr_dev = kunit_device_register(test, "fpga-manager-test-dev"); in fpga_region_test_init()
167 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->mgr_dev); in fpga_region_test_init()
169 ctx->mgr = devm_fpga_mgr_register(ctx->mgr_dev, "Fake FPGA Manager", in fpga_region_test_init()
170 &fake_mgr_ops, &ctx->mgr_stats); in fpga_region_test_init()
171 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); in fpga_region_test_init()
173 ctx->bridge_dev = kunit_device_register(test, "fpga-bridge-test-dev"); in fpga_region_test_init()
174 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->bridge_dev); in fpga_region_test_init()
176 ctx->bridge = fpga_bridge_register(ctx->bridge_dev, "Fake FPGA Bridge", in fpga_region_test_init()
177 &fake_bridge_ops, &ctx->bridge_stats); in fpga_region_test_init()
178 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); in fpga_region_test_init()
180 ctx->bridge_stats.enable = true; in fpga_region_test_init()
182 ret = kunit_add_action_or_reset(test, fpga_bridge_unregister_wrapper, ctx->bridge); in fpga_region_test_init()
185 ctx->region_dev = kunit_device_register(test, "fpga-region-test-dev"); in fpga_region_test_init()
186 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->region_dev); in fpga_region_test_init()
188 region_info.mgr = ctx->mgr; in fpga_region_test_init()
189 region_info.priv = ctx->bridge; in fpga_region_test_init()
192 ctx->region = fpga_region_register_full(ctx->region_dev, ®ion_info); in fpga_region_test_init()
193 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->region)); in fpga_region_test_init()
195 ret = kunit_add_action_or_reset(test, fpga_region_unregister_wrapper, ctx->region); in fpga_region_test_init()
198 test->priv = ctx; in fpga_region_test_init()