1 // SPDX-License-Identifier: GPL-2.0
3  * FPGA Manager Driver for Altera SOCFPGA
5  *  Copyright (C) 2013-2015 Altera Corporation
9 #include <linux/fpga/fpga-mgr.h>
96 /* In power-up order. Reverse for power-down. */
98 	"FPGA-1.5V",
99 	"FPGA-1.1V",
100 	"FPGA-2.5V",
120 	[MSEL_PP16_FAST_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
121 	[MSEL_PP16_FAST_AES_NODC] =   { CFGWDTH_16 | CDRATIO_X2, 1 },
122 	[MSEL_PP16_FAST_AESOPT_DC] =  { CFGWDTH_16 | CDRATIO_X4, 1 },
123 	[MSEL_PP16_SLOW_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
124 	[MSEL_PP16_SLOW_AES_NODC] =   { CFGWDTH_16 | CDRATIO_X2, 1 },
125 	[MSEL_PP16_SLOW_AESOPT_DC] =  { CFGWDTH_16 | CDRATIO_X4, 1 },
126 	[MSEL_PP32_FAST_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
127 	[MSEL_PP32_FAST_AES_NODC] =   { CFGWDTH_32 | CDRATIO_X4, 1 },
128 	[MSEL_PP32_FAST_AESOPT_DC] =  { CFGWDTH_32 | CDRATIO_X8, 1 },
129 	[MSEL_PP32_SLOW_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
130 	[MSEL_PP32_SLOW_AES_NODC] =   { CFGWDTH_32 | CDRATIO_X4, 1 },
131 	[MSEL_PP32_SLOW_AESOPT_DC] =  { CFGWDTH_32 | CDRATIO_X8, 1 },
136 	return readl(priv->fpga_base_addr + reg_offset);  in socfpga_fpga_readl()
142 	writel(value, priv->fpga_base_addr + reg_offset);  in socfpga_fpga_writel()
148 	return __raw_readl(priv->fpga_base_addr + reg_offset);  in socfpga_fpga_raw_readl()
154 	__raw_writel(value, priv->fpga_base_addr + reg_offset);  in socfpga_fpga_raw_writel()
159 	writel(value, priv->fpga_data_addr);  in socfpga_fpga_data_writel()
229 		udelay(1);  in socfpga_fpga_dclk_set_and_wait_clear()
230 	} while (timeout--);  in socfpga_fpga_dclk_set_and_wait_clear()
232 	return -ETIMEDOUT;  in socfpga_fpga_dclk_set_and_wait_clear()
248 	} while (timeout--);  in socfpga_fpga_wait_for_state()
250 	return -ETIMEDOUT;  in socfpga_fpga_wait_for_state()
296 		complete(&priv->status_complete);  in socfpga_fpga_isr()
308 	init_completion(&priv->status_complete);  in socfpga_fpga_wait_for_config_done()
312 						&priv->status_complete,  in socfpga_fpga_wait_for_config_done()
315 		ret = -ETIMEDOUT;  in socfpga_fpga_wait_for_config_done()
331 		return -EINVAL;  in socfpga_fpga_cfg_mode_get()
361 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_reset()
366 	 * Step 1:  in socfpga_fpga_reset()
367 	 *  - Set CTRL.CFGWDTH, CTRL.CDRATIO to match cfg mode  in socfpga_fpga_reset()
368 	 *  - Set CTRL.NCE to 0  in socfpga_fpga_reset()
374 	/* Step 2: Set CTRL.EN to 1 */  in socfpga_fpga_reset()
378 	/* Step 3: Set CTRL.NCONFIGPULL to 1 to put FPGA in reset */  in socfpga_fpga_reset()
383 	/* Step 4: Wait for STATUS.MODE to report FPGA is in reset phase */  in socfpga_fpga_reset()
386 	/* Step 5: Set CONTROL.NCONFIGPULL to 0 to release FPGA from reset */  in socfpga_fpga_reset()
392 		return -ETIMEDOUT;  in socfpga_fpga_reset()
398  * Prepare the FPGA to receive the configuration data.
404 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_ops_configure_init()
407 	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {  in socfpga_fpga_ops_configure_init()
408 		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");  in socfpga_fpga_ops_configure_init()
409 		return -EINVAL;  in socfpga_fpga_ops_configure_init()
411 	/* Steps 1 - 5: Reset the FPGA */  in socfpga_fpga_ops_configure_init()
416 	/* Step 6: Wait for FPGA to enter configuration phase */  in socfpga_fpga_ops_configure_init()
418 		return -ETIMEDOUT;  in socfpga_fpga_ops_configure_init()
424 	/* Step 8: Set CTRL.AXICFGEN to 1 to enable transfer of config data */  in socfpga_fpga_ops_configure_init()
432  * Step 9: write data to the FPGA data register
437 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_ops_configure_write()
442 		return -EINVAL;  in socfpga_fpga_ops_configure_write()
444 	/* Write out the complete 32-bit chunks. */  in socfpga_fpga_ops_configure_write()
447 		count -= sizeof(u32);  in socfpga_fpga_ops_configure_write()
450 	/* Write out remaining non 32-bit chunks. */  in socfpga_fpga_ops_configure_write()
458 	case 1:  in socfpga_fpga_ops_configure_write()
465 		return -EFAULT;  in socfpga_fpga_ops_configure_write()
474 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_ops_configure_complete()
479 	 *  - Observe CONF_DONE and nSTATUS (active low)  in socfpga_fpga_ops_configure_complete()
480 	 *  - if CONF_DONE = 1 and nSTATUS = 1, configuration was successful  in socfpga_fpga_ops_configure_complete()
481 	 *  - if CONF_DONE = 0 and nSTATUS = 0, configuration failed  in socfpga_fpga_ops_configure_complete()
493 	 *  - Write 4 to DCLKCNT  in socfpga_fpga_ops_configure_complete()
494 	 *  - Wait for STATUS.DCNTDONE = 1  in socfpga_fpga_ops_configure_complete()
495 	 *  - Clear W1C bit in STATUS.DCNTDONE  in socfpga_fpga_ops_configure_complete()
498 		return -ETIMEDOUT;  in socfpga_fpga_ops_configure_complete()
502 		return -ETIMEDOUT;  in socfpga_fpga_ops_configure_complete()
511 /* Translate state register values to FPGA framework state */
523 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_ops_state()
546 	struct device *dev = &pdev->dev;  in socfpga_fpga_probe()
553 		return -ENOMEM;  in socfpga_fpga_probe()
555 	priv->fpga_base_addr = devm_platform_ioremap_resource(pdev, 0);  in socfpga_fpga_probe()
556 	if (IS_ERR(priv->fpga_base_addr))  in socfpga_fpga_probe()
557 		return PTR_ERR(priv->fpga_base_addr);  in socfpga_fpga_probe()
559 	priv->fpga_data_addr = devm_platform_ioremap_resource(pdev, 1);  in socfpga_fpga_probe()
560 	if (IS_ERR(priv->fpga_data_addr))  in socfpga_fpga_probe()
561 		return PTR_ERR(priv->fpga_data_addr);  in socfpga_fpga_probe()
563 	priv->irq = platform_get_irq(pdev, 0);  in socfpga_fpga_probe()
564 	if (priv->irq < 0)  in socfpga_fpga_probe()
565 		return priv->irq;  in socfpga_fpga_probe()
567 	ret = devm_request_irq(dev, priv->irq, socfpga_fpga_isr, 0,  in socfpga_fpga_probe()
572 	mgr = devm_fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",  in socfpga_fpga_probe()
579 	{ .compatible = "altr,socfpga-fpga-mgr", },
597 MODULE_DESCRIPTION("Altera SOCFPGA FPGA Manager");