1 // SPDX-License-Identifier: GPL-2.0
3  * FPGA Manager Driver for FPGA Management Engine (FME)
5  * Copyright (C) 2017-2018 Intel Corporation, Inc.
22 #include <linux/io-64-nonatomic-lo-hi.h>
23 #include <linux/fpga/fpga-mgr.h>
25 #include "dfl-fme-pr.h"
39 #define FME_PR_CTRL_PR_RGN_ID	GENMASK_ULL(9, 7)       /* PR Region ID */
52 /* PR data from the raw-binary file. */
111 	struct device *dev = &mgr->dev;  in fme_mgr_write_init()
112 	struct fme_mgr_priv *priv = mgr->priv;  in fme_mgr_write_init()
113 	void __iomem *fme_pr = priv->ioaddr;  in fme_mgr_write_init()
116 	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {  in fme_mgr_write_init()
118 		return -EINVAL;  in fme_mgr_write_init()
131 		return -ETIMEDOUT;  in fme_mgr_write_init()
145 		priv->pr_error = fme_mgr_pr_error_handle(fme_pr);  in fme_mgr_write_init()
146 		return -ETIMEDOUT;  in fme_mgr_write_init()
150 	priv->pr_error = fme_mgr_pr_error_handle(fme_pr);  in fme_mgr_write_init()
151 	if (priv->pr_error)  in fme_mgr_write_init()
153 			(unsigned long long)priv->pr_error);  in fme_mgr_write_init()
159 	pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);  in fme_mgr_write_init()
168 	struct device *dev = &mgr->dev;  in fme_mgr_write()
169 	struct fme_mgr_priv *priv = mgr->priv;  in fme_mgr_write()
170 	void __iomem *fme_pr = priv->ioaddr;  in fme_mgr_write()
195 				return -ETIMEDOUT;  in fme_mgr_write()
205 			return -EINVAL;  in fme_mgr_write()
212 		count -= 4;  in fme_mgr_write()
213 		pr_credit--;  in fme_mgr_write()
223 	struct device *dev = &mgr->dev;  in fme_mgr_write_complete()
224 	struct fme_mgr_priv *priv = mgr->priv;  in fme_mgr_write_complete()
225 	void __iomem *fme_pr = priv->ioaddr;  in fme_mgr_write_complete()
239 		return -ETIMEDOUT;  in fme_mgr_write_complete()
243 	priv->pr_error = fme_mgr_pr_error_handle(fme_pr);  in fme_mgr_write_complete()
244 	if (priv->pr_error) {  in fme_mgr_write_complete()
246 			(unsigned long long)priv->pr_error);  in fme_mgr_write_complete()
247 		return -EIO;  in fme_mgr_write_complete()
257 	struct fme_mgr_priv *priv = mgr->priv;  in fme_mgr_status()
259 	return pr_error_to_mgr_status(priv->pr_error);  in fme_mgr_status()
272 	id->id_l = readq(fme_pr + FME_PR_INTFC_ID_L);  in fme_mgr_get_compat_id()
273 	id->id_h = readq(fme_pr + FME_PR_INTFC_ID_H);  in fme_mgr_get_compat_id()
278 	struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);  in fme_mgr_probe()
280 	struct device *dev = &pdev->dev;  in fme_mgr_probe()
286 		return -ENOMEM;  in fme_mgr_probe()
288 	if (pdata->ioaddr)  in fme_mgr_probe()
289 		priv->ioaddr = pdata->ioaddr;  in fme_mgr_probe()
291 	if (!priv->ioaddr) {  in fme_mgr_probe()
292 		priv->ioaddr = devm_platform_ioremap_resource(pdev, 0);  in fme_mgr_probe()
293 		if (IS_ERR(priv->ioaddr))  in fme_mgr_probe()
294 			return PTR_ERR(priv->ioaddr);  in fme_mgr_probe()
297 	info.name = "DFL FME FPGA Manager";  in fme_mgr_probe()
302 		return -ENOMEM;  in fme_mgr_probe()
304 	fme_mgr_get_compat_id(priv->ioaddr, info.compat_id);  in fme_mgr_probe()
318 MODULE_DESCRIPTION("FPGA Manager for DFL FPGA Management Engine");
321 MODULE_ALIAS("platform:dfl-fme-mgr");