Lines Matching +full:generic +full:- +full:2
1 /* SPDX-License-Identifier: BSD-3-Clause */
7 * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details
9 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/
15 /* Generic Messages */
62 /* PSI-L requests */
91 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
112 * struct ti_sci_msg_resp_version - Response for a message
113 * @hdr: Generic header
123 * Response to a generic message with message type TI_SCI_MSG_VERSION
134 * struct ti_sci_msg_req_reboot - Reboot the SoC
135 * @hdr: Generic Header
137 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
145 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps
146 * @hdr: Generic header
148 * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported)
154 * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
170 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
171 * @hdr: Generic header
177 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
181 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
182 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
188 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
192 /* Additional hdr->flags options */
202 #define MSG_DEVICE_SW_STATE_ON 2
207 * struct ti_sci_msg_req_get_device_state - Request to get device.
208 * @hdr: Generic header
220 * struct ti_sci_msg_resp_get_device_state - Response to get device request.
221 * @hdr: Generic header
227 * - Uses the MSG_DEVICE_SW_* macros
239 #define MSG_DEVICE_HW_STATE_TRANS 2
244 * struct ti_sci_msg_req_set_device_resets - Set the desired resets
246 * @hdr: Generic header
253 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
263 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
264 * @hdr: Generic Header, Certain flags can be set specific to the clocks:
271 * is only applicable to clock inputs on the SoC pseudo-device.
296 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
300 /* Additional hdr->flags options */
309 #define MSG_CLOCK_SW_STATE_REQ 2
315 * struct ti_sci_msg_req_get_clock_state - Request for clock state
316 * @hdr: Generic Header
337 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
338 * @hdr: Generic Header
356 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
357 * @hdr: Generic Header
369 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
382 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
383 * @hdr: Generic Header
402 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
403 * @hdr: Generic Header
418 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
419 * @hdr: Generic header
440 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
441 * @hdr: Generic header
457 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
458 * @hdr: Generic Header
491 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
492 * @hdr: Generic Header
504 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
505 * @hdr: Generic Header
529 * Calling set frequency on a clock input to the SoC pseudo-device will
533 * Calling set frequency on clock outputs from the SoC pseudo-device will
536 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
550 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
551 * @hdr: Generic Header
571 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
572 * @hdr: Generic Header
583 * struct tisci_msg_req_prepare_sleep - Request for TISCI_MSG_PREPARE_SLEEP.
587 * @ctx_lo Low 32-bits of physical pointer to address to use for context save.
588 * @ctx_hi High 32-bits of physical pointer to address to use for context save.
594 * easily shared from the application, as this is a non-secure message and
613 * struct tisci_msg_set_io_isolation_req - Request for TI_SCI_MSG_SET_IO_ISOLATION.
615 * @hdr: Generic header
619 * Response is generic ACK / NACK message.
627 * struct ti_sci_msg_resp_lpm_wake_reason - Response for TI_SCI_MSG_LPM_WAKE_REASON.
629 * @hdr: Generic header.
636 * Response to a generic message with message type TI_SCI_MSG_LPM_WAKE_REASON,
645 u32 rsvd[2];
649 * struct ti_sci_msg_req_lpm_set_device_constraint - Request for
661 * is a non-secure message and therefore can be sent by anyone. By setting a
671 u32 rsvd[2];
675 * struct ti_sci_msg_req_lpm_set_latency_constraint - Request for
688 * from the application, as this is a non-secure message and therefore can be sent by
702 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
704 * @hdr: Generic Header
725 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
726 * @hdr: Generic Header
743 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route
745 * @hdr: Generic Header
750 * 0 - Valid bit for @dst_id
751 * 1 - Valid bit for @dst_host_irq
752 * 2 - Valid bit for @ia_id
753 * 3 - Valid bit for @vint
754 * 4 - Valid bit for @global_event
755 * 5 - Valid bit for @vint_status_bit_index
756 * 31 - Valid bit for @secondary_host
775 * Response is generic ACK / NACK message.
781 #define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2)
799 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
801 * Configures the non-real-time registers of a Navigator Subsystem ring.
802 * @hdr: Generic Header
807 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
808 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
809 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
810 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
811 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
812 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
813 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid
814 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL
825 * the formula (log2(size_bytes) - 2), where size_bytes cannot be
848 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
850 * @hdr: Generic Header
851 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
853 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
859 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
860 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
867 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
878 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
880 * @hdr: Generic Header
881 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
883 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
888 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
889 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
895 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
906 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
908 * @hdr: Generic Header
911 * @flow_index: UDMAP receive flow index for non-optional configuration.
922 * 0 - end of packet descriptor
923 * 1 - Beginning of the data buffer
937 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2.
970 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive
972 * @hdr: Generic Header
979 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2.
983 * threshold 2.
1005 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
1010 * @hdr: Generic Header
1016 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
1017 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
1018 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
1019 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
1020 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
1021 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
1022 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
1023 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
1024 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
1025 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
1026 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
1027 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
1028 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
1029 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
1030 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
1031 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
1032 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
1062 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
1099 * 0 - Return immediately
1100 * 1 - Wait for completion message from remote peer
1103 * 0 - the channel is split tx channel (tchan)
1104 * 1 - the channel is block copy channel (bchan)
1133 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
1138 * @hdr: Generic Header
1145 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
1146 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
1147 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
1148 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
1149 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
1150 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
1151 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
1152 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
1153 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
1154 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
1155 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
1156 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
1157 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
1158 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
1164 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
1253 * Configuration does not include the flow registers which handle size-based
1265 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1266 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
1267 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
1268 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
1269 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
1270 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
1271 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
1272 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
1273 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
1274 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
1275 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
1276 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
1277 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
1278 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
1279 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
1280 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
1281 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
1282 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
1283 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
1288 * @flow_index: UDMAP receive flow index for non-optional configuration.
1310 * this field are 0-255 bytes.
1376 * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1422 * struct ti_sci_msg_req_proc_request - Request a processor
1423 * @hdr: Generic Header
1426 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
1435 * struct ti_sci_msg_req_proc_release - Release a processor
1436 * @hdr: Generic Header
1439 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
1448 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
1449 * @hdr: Generic Header
1453 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
1468 * struct ti_sci_msg_req_set_config - Set Processor boot configuration
1469 * @hdr: Generic Header
1480 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
1493 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags
1494 * @hdr: Generic Header
1503 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK
1514 * struct ti_sci_msg_req_get_status - Processor boot status request
1515 * @hdr: Generic Header
1527 * struct ti_sci_msg_resp_get_status - Processor boot status response
1528 * @hdr: Generic Header