Lines Matching full:configuration

245  *				configuration of the device
803  * @valid_params: Bitfield defining validity of ring configuration parameters.
804  *	The ring configuration fields are not valid, and will not be used for
805  *	ring configuration, if their corresponding valid bit is zero.
906  * struct ti_sci_msg_udmap_rx_flow_cfg -  UDMAP receive flow configuration
911  * @flow_index: UDMAP receive flow index for non-optional configuration.
915  * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
971  *						flow optional configuration
975  * @flow_index: UDMAP receive flow index for optional configuration.
1007  * in the TISCI header via the RM board configuration resource assignment
1012  * @valid_params: Bitfield defining validity of tx channel configuration
1013  * parameters. The tx channel configuration fields are not valid, and will not
1014  * be used for ch configuration, if their corresponding valid bit is zero.
1038  * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
1043  * configuration to be programmed into the tx_filt_einfo field of the
1047  * configuration to be programmed into the tx_filt_pswords field of the
1051  * interpretation configuration to be programmed into the tx_atype field of
1055  * passing mechanism configuration to be programmed into the tx_chan_type
1059  * configuration to be programmed into the tx_supr_tdpkt field of the channel's
1063  * fetch configuration to be programmed into the tx_fetch_size field of the
1068  * configuration to be programmed into the count field of the TCHAN_TCREDIT
1071  * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
1074  * requesting configuration of the transmit channel.
1085  * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
1091  * configuration to be programmed into the priority field of the channel's
1094  * @tx_burst_size: UDMAP transmit channel burst size configuration to be
1097  * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
1135  * in the TISCI header via the RM board configuration resource assignment
1140  * @valid_params: Bitfield defining validity of rx channel configuration
1142  * The rx channel configuration fields are not valid, and will not be used for
1143  * ch configuration, if their corresponding valid bit is zero.
1165  * fetch configuration to be programmed into the rx_fetch_size field of the
1168  * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1171  * of the host, requesting configuration of the receive channel.
1183  * configuration to be programmed into the priority field of the channel's
1187  * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1194  * host, requesting configuration of the receive channel.
1196  * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1205  * subordinate of the host, requesting configuration of the receive channel.
1207  * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1212  * interpretation configuration to be programmed into the rx_atype field of the
1216  * mechanism configuration to be programmed into the rx_chan_type field of the
1219  * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1222  * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1225  * @rx_burst_size: UDMAP receive channel burst size configuration to be
1253  * Configuration does not include the flow registers which handle size-based
1257  * the RM board configuration resource assignment range list.
1262  * Bitfield defining validity of rx flow configuration parameters.  The
1263  * rx flow configuration fields are not valid, and will not be used for flow
1264  * configuration, if their corresponding valid bit is zero.  Valid bit usage:
1288  * @flow_index: UDMAP receive flow index for non-optional configuration.
1291  * UDMAP receive flow extended packet info present configuration to be
1295  * UDMAP receive flow PS words present configuration to be programmed into the
1299  * UDMAP receive flow error handling configuration to be programmed into the
1303  * UDMAP receive flow descriptor type configuration to be programmed into the
1307  * UDMAP receive flow start of packet offset configuration to be programmed
1313  * UDMAP receive flow destination queue configuration to be programmed into the
1317  * configuration of the receive flow.
1320  * UDMAP receive flow source tag high byte constant configuration to be
1325  * UDMAP receive flow source tag low byte constant configuration to be
1330  * UDMAP receive flow destination tag high byte constant configuration to be
1335  * UDMAP receive flow destination tag low byte constant configuration to be
1340  * UDMAP receive flow source tag high byte selector configuration to be
1345  * UDMAP receive flow source tag low byte selector configuration to be
1350  * UDMAP receive flow destination tag high byte selector configuration to be
1355  * UDMAP receive flow destination tag low byte selector configuration to be
1360  * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1365  * configuration of the receive flow.
1368  * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1373  * configuration of the receive flow.
1376  * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1381  * configuration of the receive flow.
1384  * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1389  * configuration of the receive flow.
1392  * UDMAP receive flow PS words location configuration to be programmed into the
1468  * struct ti_sci_msg_req_set_config - Set Processor boot configuration