48 	int ret = 0;  in decode_register()
68 #define L2C_CTL			0x87E080800000
69 #define L2C_CTL_DISIDXALIAS	BIT(0)
71 #define PCI_DEVICE_ID_THUNDER_LMC 0xa022
73 #define LMC_FADR		0x20
74 #define LMC_FADR_FDIMM(x)	((x >> 37) & 0x1)
75 #define LMC_FADR_FBUNK(x)	((x >> 36) & 0x1)
76 #define LMC_FADR_FBANK(x)	((x >> 32) & 0xf)
77 #define LMC_FADR_FROW(x)	((x >> 14) & 0xffff)
78 #define LMC_FADR_FCOL(x)	((x >> 0) & 0x1fff)
80 #define LMC_NXM_FADR		0x28
81 #define LMC_ECC_SYND		0x38
83 #define LMC_ECC_PARITY_TEST	0x108
85 #define LMC_INT_W1S		0x150
87 #define LMC_INT_ENA_W1C		0x158
88 #define LMC_INT_ENA_W1S		0x160
90 #define LMC_CONFIG		0x188
94 #define LMC_CONFIG_PBANK_LSB(x)	(((x) >> 5) & 0xF)
95 #define LMC_CONFIG_ROW_LSB(x)	(((x) >> 2) & 0x7)
97 #define LMC_CONTROL		0x190
100 #define LMC_INT			0x1F0
103 #define LMC_INT_DED_ERR		(0xFUL << 5)
104 #define LMC_INT_SEC_ERR         (0xFUL << 1)
105 #define LMC_INT_NXM_WR_MASK	BIT(0)
107 #define LMC_DDR_PLL_CTL		0x258
110 #define LMC_FADR_SCRAMBLED	0x330
138 	{0, 0, NULL},
146 #define LMC_INT_INTR_NXM_WR_ENA		BIT(0)
148 #define LMC_INT_ENA_ALL			GENMASK(5, 0)
150 #define LMC_DDR_PLL_CTL		0x258
153 #define LMC_CONTROL		0x190
154 #define LMC_CONTROL_RDIMM	BIT(0)
156 #define LMC_SCRAM_FADR		0x330
158 #define LMC_CHAR_MASK0		0x228
159 #define LMC_CHAR_MASK2		0x238
230 	snprintf(buf, count, "0x%016llx", pdata->_field);		    \
242 	res = kstrtoull_from_user(data, count, 0, &pdata->_field);	    \
259 	sprintf(buf, "0x%016llx", readq(pdata->regs + _reg));		    \
272 	res = kstrtoull_from_user(data, count, 0, &val);		    \
293  *	echo 0x802 > /sys/kernel/debug/<device number>/ecc_parity_test
305 	res = kstrtoull_from_user(data, count, 0, &val);  in thunderx_lmc_inject_int_write()
324 	snprintf(buf, sizeof(buf), "0x%016llx", lmc_int);  in thunderx_lmc_int_read()
328 #define TEST_PATTERN 0xa5
341 	cl_idx = (phys & 0x7f) >> 4;  in inject_ecc_fn()
353 	for (i = 0; i < lines; i++) {  in inject_ecc_fn()
361 		asm volatile("dc civac, %0\n"  in inject_ecc_fn()
366 	for (i = 0; i < lines; i++) {  in inject_ecc_fn()
372 		__asm__ volatile("sys #0,c11,C1,#2, %0\n"  in inject_ecc_fn()
376 	for (i = 0; i < lines; i++) {  in inject_ecc_fn()
382 		__asm__ volatile("sys #0,c11,C1,#1, %0"  in inject_ecc_fn()
386 	for (i = 0; i < lines; i++) {  in inject_ecc_fn()
392 		asm volatile("dc ivac, %0\n"  in inject_ecc_fn()
397 	return 0;  in inject_ecc_fn()
410 	atomic_set(&lmc->ecc_int, 0);  in thunderx_lmc_inject_ecc_write()
412 	lmc->mem = alloc_pages_node(lmc->node, GFP_KERNEL, 0);  in thunderx_lmc_inject_ecc_write()
418 		__free_pages(lmc->mem, 0);  in thunderx_lmc_inject_ecc_write()
427 		for (offs = 0; offs < PAGE_SIZE; offs += cline_size) {  in thunderx_lmc_inject_ecc_write()
438 	__free_pages(lmc->mem, 0);  in thunderx_lmc_inject_ecc_write()
469 		return 0;  in thunderx_create_debugfs_nodes()
474 	for (i = 0; i < num; i++) {  in thunderx_create_debugfs_nodes()
487 	phys_addr_t addr = 0;  in thunderx_faddr_to_phys()
516 	unsigned int number = 0;  in thunderx_get_num_lmcs()
547 	writeq(0, lmc->regs + LMC_CHAR_MASK0);  in thunderx_lmc_err_isr()
548 	writeq(0, lmc->regs + LMC_CHAR_MASK2);  in thunderx_lmc_err_isr()
549 	writeq(0x2, lmc->regs + LMC_ECC_PARITY_TEST);  in thunderx_lmc_err_isr()
621 					     0, -1, -1, -1, msg, other);  in thunderx_lmc_threaded_isr()
626 					     0, -1, -1, -1, msg, other);  in thunderx_lmc_threaded_isr()
642 	{ 0, },
650 	ret += max(node, 0) << 3;  in pci_dev_to_mc_idx()
676 	ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_lmc");  in thunderx_lmc_probe()
692 	lmc->regs = pcim_iomap_table(pdev)[0];  in thunderx_lmc_probe()
717 	lmc->msix_ent.entry = 0;  in thunderx_lmc_probe()
719 	lmc->ring_head = 0;  in thunderx_lmc_probe()
720 	lmc->ring_tail = 0;  in thunderx_lmc_probe()
730 					thunderx_lmc_threaded_isr, 0,  in thunderx_lmc_probe()
737 	lmc->node = FIELD_GET(THUNDERX_NODE, pci_resource_start(pdev, 0));  in thunderx_lmc_probe()
743 	lmc->pbank_lsb = (lmc_config >> 5) & 0xf;  in thunderx_lmc_probe()
746 	lmc->rank_lsb -= FIELD_GET(LMC_CONFIG_RANK_ENA, lmc_config) ? 1 : 0;  in thunderx_lmc_probe()
784 				 ret, ret >= 0 ? " created" : "");  in thunderx_lmc_probe()
788 	return 0;  in thunderx_lmc_probe()
819 #define PCI_DEVICE_ID_THUNDER_OCX 0xa013
826 #define OCX_COM_INT		0x100
827 #define OCX_COM_INT_W1S		0x108
828 #define OCX_COM_INT_ENA_W1S	0x110
829 #define OCX_COM_INT_ENA_W1C	0x118
836 #define OCX_COM_RX_LANE			GENMASK(23, 0)
870 	{0, 0, NULL},
873 #define OCX_COM_LINKX_INT(x)		(0x120 + (x) * 8)
874 #define OCX_COM_LINKX_INT_W1S(x)	(0x140 + (x) * 8)
875 #define OCX_COM_LINKX_INT_ENA_W1S(x)	(0x160 + (x) * 8)
876 #define OCX_COM_LINKX_INT_ENA_W1C(x)	(0x180 + (x) * 8)
891 #define OCX_COM_LINK_REPLAY_SBE			BIT(0)
944 	{0, 0, NULL},
959 #define OCX_LNE_INT(x)			(0x8018 + (x) * 0x100)
960 #define OCX_LNE_INT_EN(x)		(0x8020 + (x) * 0x100)
961 #define OCX_LNE_BAD_CNT(x)		(0x8028 + (x) * 0x100)
962 #define OCX_LNE_CFG(x)			(0x8000 + (x) * 0x100)
963 #define OCX_LNE_STAT(x, y)		(0x8040 + (x) * 0x100 + (y) * 8)
968 #define OCX_LNE_CFG_RX_STAT_ENA			BIT(0)
977 #define OCX_LANE_SERDES_LOCK_LOSS		BIT(0)
979 #define OCX_COM_LANE_INT_UE       (0)
1024 	{0, 0, NULL},
1027 #define OCX_LNE_INT_ENA_ALL		(GENMASK(9, 8) | GENMASK(6, 0))
1028 #define OCX_COM_INT_ENA_ALL		(GENMASK(54, 50) | GENMASK(23, 0))
1030 					 GENMASK(9, 7) | GENMASK(5, 0))
1032 #define OCX_TLKX_ECC_CTL(x)		(0x10018 + (x) * 0x2000)
1033 #define OCX_RLKX_ECC_CTL(x)		(0x18018 + (x) * 0x2000)
1082 	for (lane = 0; lane < OCX_RX_LANES; lane++) {  in thunderx_ocx_com_isr()
1132 		for (lane = 0; lane < OCX_RX_LANES; lane++)  in thunderx_ocx_com_threaded_isr()
1148 			edac_device_handle_ce(ocx->edac_dev, 0, 0, msg);  in thunderx_ocx_com_threaded_isr()
1217 			edac_device_handle_ue(ocx->edac_dev, 0, 0, msg);  in thunderx_ocx_lnk_threaded_isr()
1219 			edac_device_handle_ce(ocx->edac_dev, 0, 0, msg);  in thunderx_ocx_lnk_threaded_isr()
1234 OCX_DEBUGFS_ATTR(tlk0_ecc_ctl, OCX_TLKX_ECC_CTL(0));
1238 OCX_DEBUGFS_ATTR(rlk0_ecc_ctl, OCX_RLKX_ECC_CTL(0));
1242 OCX_DEBUGFS_ATTR(com_link0_int, OCX_COM_LINKX_INT_W1S(0));
1246 OCX_DEBUGFS_ATTR(lne00_badcnt, OCX_LNE_BAD_CNT(0));
1318 	{ 0, },
1325 	for (lane = 0; lane < OCX_RX_LANES; lane++) {  in thunderx_ocx_clearstats()
1331 		for (stat = 0; stat < OCX_RX_LANE_STATS; stat++)  in thunderx_ocx_clearstats()
1353 	ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_ocx");  in thunderx_ocx_probe()
1362 					      name, 1, "CCPI", 1, 0, idx);  in thunderx_ocx_probe()
1369 	ocx->com_ring_head = 0;  in thunderx_ocx_probe()
1370 	ocx->com_ring_tail = 0;  in thunderx_ocx_probe()
1371 	ocx->link_ring_head = 0;  in thunderx_ocx_probe()
1372 	ocx->link_ring_tail = 0;  in thunderx_ocx_probe()
1374 	ocx->regs = pcim_iomap_table(pdev)[0];  in thunderx_ocx_probe()
1383 	for (i = 0; i < OCX_INTS; i++) {  in thunderx_ocx_probe()
1385 		ocx->msix_ent[i].vector = 0;  in thunderx_ocx_probe()
1394 	for (i = 0; i < OCX_INTS; i++) {  in thunderx_ocx_probe()
1403 						0, "[EDAC] ThunderX OCX",  in thunderx_ocx_probe()
1429 				 ret, ret >= 0 ? " created" : "");  in thunderx_ocx_probe()
1437 	for (i = 0; i < OCX_RX_LANES; i++) {  in thunderx_ocx_probe()
1446 	for (i = 0; i < OCX_LINK_INTS; i++) {  in thunderx_ocx_probe()
1459 	return 0;  in thunderx_ocx_probe()
1474 	for (i = 0; i < OCX_INTS; i++) {  in thunderx_ocx_remove()
1496 #define PCI_DEVICE_ID_THUNDER_L2C_TAD 0xa02e
1497 #define PCI_DEVICE_ID_THUNDER_L2C_CBC 0xa02f
1498 #define PCI_DEVICE_ID_THUNDER_L2C_MCI 0xa030
1500 #define L2C_TAD_INT_W1C		0x40000
1501 #define L2C_TAD_INT_W1S		0x40008
1503 #define L2C_TAD_INT_ENA_W1C	0x40020
1504 #define L2C_TAD_INT_ENA_W1S	0x40028
1607 	{0, 0, NULL},
1623 #define L2C_TAD_TIMETWO		0x50000
1624 #define L2C_TAD_TIMEOUT		0x50100
1625 #define L2C_TAD_ERR		0x60000
1626 #define L2C_TAD_TQD_ERR		0x60100
1627 #define L2C_TAD_TTG_ERR		0x60200
1630 #define L2C_CBC_INT_W1C		0x60000
1632 #define L2C_CBC_INT_RSDSBE	 BIT(0)
1683 	{0, 0, NULL},
1686 #define L2C_CBC_INT_W1S		0x60008
1687 #define L2C_CBC_INT_ENA_W1C	0x60020
1692 #define L2C_CBC_INT_ENA_W1S	0x60028
1694 #define L2C_CBC_IODISOCIERR	0x80008
1695 #define L2C_CBC_IOCERR		0x80010
1696 #define L2C_CBC_RSDERR		0x80018
1697 #define L2C_CBC_MIBERR		0x80020
1700 #define L2C_MCI_INT_W1C		0x0
1702 #define L2C_MCI_INT_VBFSBE	 BIT(0)
1716 	{0, 0, NULL},
1719 #define L2C_MCI_INT_W1S		0x8
1720 #define L2C_MCI_INT_ENA_W1C	0x20
1724 #define L2C_MCI_INT_ENA_W1S	0x28
1726 #define L2C_MCI_ERR		0x10000
1895 			edac_device_handle_ue(l2c->edac_dev, 0, 0, msg);  in thunderx_l2c_threaded_isr()
1897 			edac_device_handle_ce(l2c->edac_dev, 0, 0, msg);  in thunderx_l2c_threaded_isr()
1935 	{ 0, },
1958 	ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_l2c");  in thunderx_l2c_probe()
2000 					      name, 1, "L2C", 1, 0, idx);  in thunderx_l2c_probe()
2009 	l2c->regs = pcim_iomap_table(pdev)[0];  in thunderx_l2c_probe()
2018 	l2c->ring_head = 0;  in thunderx_l2c_probe()
2019 	l2c->ring_tail = 0;  in thunderx_l2c_probe()
2021 	l2c->msix_ent.entry = 0;  in thunderx_l2c_probe()
2022 	l2c->msix_ent.vector = 0;  in thunderx_l2c_probe()
2033 					0, "[EDAC] ThunderX L2C",  in thunderx_l2c_probe()
2057 				 ret, ret >= 0 ? " created" : "");  in thunderx_l2c_probe()
2065 	return 0;  in thunderx_l2c_probe()
2107 	int rc = 0;  in thunderx_edac_init()