Lines Matching +full:per +full:- +full:channel
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
33 #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
55 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
63 * cccc = channel
67 * Errors from either the memory of the 1-level memory system or the
68 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
73 * of the 2-level memory system.
77 /* Max RRL register sets per {,sub-,pseudo-}channel. */
79 /* Max RRL registers per set. */
96 /* RRL registers per {,sub-,pseudo-}channel. */
102 /* RRL register widths in byte per set. */
104 /* RRL control bits of the first register per set. */
138 int num_channels; /* channels per memory controller */
139 int num_dimms; /* dimms per channel */
158 * Two groups of RRL control registers per channel to save default RRL
159 * settings of two {sub-,pseudo-}channels in Linux RRL control mode.
216 int channel; member
244 /* DDR memory controllers per socket */
246 /* DDR channels per DDR memory controller */
248 /* DDR DIMMs per DDR memory channel */
250 /* Per DDR channel memory-mapped I/O size */
252 /* HBM memory controllers per socket */
254 /* HBM channels per HBM memory controller */
256 /* HBM DIMMs per HBM memory channel */
258 /* Per HBM channel memory-mapped I/O size */
274 /* RRL register sets per DDR channel */
276 /* RRL register sets per HBM channel */