51 #define TOM_OFFSET			0xa0
53 #define TOLUD_OFFSET			0xbc
55 #define CAPID_C_OFFSET			0xec
59 #define CAPID_E_OFFSET			0xf0
64 #define ERRSTS_OFFSET			0xc8
69 #define ERRCMD_OFFSET			0xca
76 #define IBECC_ACTIVATE_EN		BIT(0)
88 #define MCHBAR_OFFSET			0x48
89 #define MCHBAR_EN			BIT_ULL(0)
91 #define MCHBAR_SIZE			0x10000
96 #define MAD_INTER_CHANNEL_DDR_TYPE(v)	GET_BITFIELD(v, 0, 2)
103 #define MAD_INTRA_CH_DIMM_L_MAP(v)	GET_BITFIELD(v, 0, 0)
106 #define MAD_DIMM_CH0_OFFSET		(IMC_BASE + 0xc)
107 #define MAD_DIMM_CH_DIMM_L_SIZE(v)	((u64)GET_BITFIELD(v, 0, 6) << 29)
113 #define MAD_MC_HASH_OFFSET		(IMC_BASE + 0x1b8)
117 #define CHANNEL_HASH_OFFSET		(IMC_BASE + 0x24)
119 #define CHANNEL_EHASH_OFFSET		(IMC_BASE + 0x28)
203 #define DID_EHL_SKU5	0x4514
204 #define DID_EHL_SKU6	0x4528
205 #define DID_EHL_SKU7	0x452a
206 #define DID_EHL_SKU8	0x4516
207 #define DID_EHL_SKU9	0x452c
208 #define DID_EHL_SKU10	0x452e
209 #define DID_EHL_SKU11	0x4532
210 #define DID_EHL_SKU12	0x4518
211 #define DID_EHL_SKU13	0x451a
212 #define DID_EHL_SKU14	0x4534
213 #define DID_EHL_SKU15	0x4536
216 #define DID_ICL_SKU8	0x4581
217 #define DID_ICL_SKU10	0x4585
218 #define DID_ICL_SKU11	0x4589
219 #define DID_ICL_SKU12	0x458d
222 #define DID_TGL_SKU	0x9a14
225 #define DID_ADL_SKU1	0x4601
226 #define DID_ADL_SKU2	0x4602
227 #define DID_ADL_SKU3	0x4621
228 #define DID_ADL_SKU4	0x4641
231 #define DID_ADL_N_SKU1	0x4614
232 #define DID_ADL_N_SKU2	0x4617
233 #define DID_ADL_N_SKU3	0x461b
234 #define DID_ADL_N_SKU4	0x461c
235 #define DID_ADL_N_SKU5	0x4673
236 #define DID_ADL_N_SKU6	0x4674
237 #define DID_ADL_N_SKU7	0x4675
238 #define DID_ADL_N_SKU8	0x4677
239 #define DID_ADL_N_SKU9	0x4678
240 #define DID_ADL_N_SKU10	0x4679
241 #define DID_ADL_N_SKU11	0x467c
242 #define DID_ADL_N_SKU12	0x4632
245 #define DID_AZB_SKU1	0x4676
248 #define DID_ASL_SKU1	0x464a
251 #define DID_RPL_P_SKU1	0xa706
252 #define DID_RPL_P_SKU2	0xa707
253 #define DID_RPL_P_SKU3	0xa708
254 #define DID_RPL_P_SKU4	0xa716
255 #define DID_RPL_P_SKU5	0xa718
258 #define DID_MTL_PS_SKU1	0x7d21
259 #define DID_MTL_PS_SKU2	0x7d22
260 #define DID_MTL_PS_SKU3	0x7d23
261 #define DID_MTL_PS_SKU4	0x7d24
264 #define DID_MTL_P_SKU1	0x7d01
265 #define DID_MTL_P_SKU2	0x7d02
266 #define DID_MTL_P_SKU3	0x7d14
269 #define DID_ARL_UH_SKU1	0x7d06
270 #define DID_ARL_UH_SKU2	0x7d20
271 #define DID_ARL_UH_SKU3	0x7d30
274 #define DID_PTL_H_SKU1	0xb000
275 #define DID_PTL_H_SKU2	0xb001
276 #define DID_PTL_H_SKU3	0xb002
279 #define DID_WCL_SKU1	0xfd00
308 	return 0;  in get_mchbar()
373 #define MCHBAR_MEMSS_IBECCDIS	0x13c00  in mtl_ps_ibecc_available()
383 		igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar);  in mtl_ps_ibecc_available()
390 	/* Bit6: 1 - IBECC is disabled, 0 - IBECC isn't disabled */  in mtl_ps_ibecc_available()
436 		GET_BITFIELD(eaddr, 0, intlv_bit - 1);  in tgl_err_addr_to_mem_addr()
475 		   GET_BITFIELD(eaddr, 0, intlv_bit - 1);  in adl_err_addr_to_imc_addr()
487 	.imc_base		= 0x5000,
488 	.ibecc_base		= 0xdc00,
490 	.ibecc_error_log_offset	= 0x170,
497 	.imc_base		= 0x5000,
498 	.ibecc_base		= 0xd800,
499 	.ibecc_error_log_offset	= 0x170,
508 	.imc_base		= 0x5000,
509 	.cmf_base		= 0x11000,
510 	.cmf_size		= 0x800,
511 	.ms_hash_offset		= 0xac,
512 	.ibecc_base		= 0xd400,
513 	.ibecc_error_log_offset	= 0x170,
522 	.imc_base		= 0xd800,
523 	.ibecc_base		= 0xd400,
524 	.ibecc_error_log_offset	= 0x68,
533 	.imc_base		= 0xd800,
534 	.ibecc_base		= 0xd400,
535 	.ibecc_error_log_offset	= 0x68,
544 	.imc_base		= 0xd800,
545 	.ibecc_base		= 0xd400,
546 	.ibecc_error_log_offset	= 0x68,
556 	.imc_base		= 0xd800,
557 	.ibecc_base		= 0xd400,
558 	.ibecc_error_log_offset	= 0x170,
567 	.imc_base		= 0xd800,
568 	.ibecc_base		= 0xd400,
569 	.ibecc_error_log_offset	= 0x170,
578 	.imc_base		= 0xd800,
579 	.ibecc_base		= 0xd400,
580 	.ibecc_error_log_offset	= 0x170,
650 	case 0:  in get_width()
666 	case 0:  in get_memory_type()
683 	u64 hash_addr = addr & mask, hash = 0;  in decode_chan_idx()
699 	channel_addr |= GET_BITFIELD(addr, 0, intlv_bit - 1);  in decode_channel_addr()
732 		edac_dbg(0, "Address 0x%llx out of range\n", addr);  in igen6_decode()
752 	return 0;  in igen6_decode()
798 	return 0;  in ecclog_gen_pool_add()
814 	 *        the invalid value ~0. This will result in a flood of invalid  in ecclog_read_and_clear()
817 	if (ecclog == ~0)  in ecclog_read_and_clear()
818 		return 0;  in ecclog_read_and_clear()
822 		return 0;  in ecclog_read_and_clear()
846 	struct igen6_imc *imc = &igen6_pvt->imc[0];  in errcmd_enable_error_reporting()
863 	return 0;  in errcmd_enable_error_reporting()
869 	int i, n = 0;  in ecclog_handler()
872 	for (i = 0; i < res_cfg->num_imc; i++) {  in ecclog_handler()
903 		memset(&res, 0, sizeof(res));  in ecclog_work_cb()
915 		edac_dbg(2, "MC %d, ecclog = 0x%llx\n", node->mc, node->ecclog);  in ecclog_work_cb()
917 		igen6_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", res.sys_addr);  in ecclog_work_cb()
930 	for (i = 0; i < res_cfg->num_imc; i++)  in ecclog_irq_work_cb()
947 	 * doesn't clear the bit NMI_REASON_CLEAR_SERR (in port 0x61) to  in ecclog_nmi_handler()
974 	if ((mce->status & 0xefff) >> 7 != 1)  in ecclog_mce_handler()
982 	edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n",  in ecclog_mce_handler()
985 	edac_dbg(0, "TSC 0x%llx\n", mce->tsc);  in ecclog_mce_handler()
986 	edac_dbg(0, "ADDR 0x%llx\n", mce->addr);  in ecclog_mce_handler()
987 	edac_dbg(0, "MISC 0x%llx\n", mce->misc);  in ecclog_mce_handler()
988 	edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n",  in ecclog_mce_handler()
1037 	for (i = 0; i < NUM_CHANNELS; i++) {  in igen6_get_dimm_config()
1046 		ndimms = 0;  in igen6_get_dimm_config()
1048 		for (j = 0; j < NUM_DIMMS; j++) {  in igen6_get_dimm_config()
1049 			dimm = edac_get_dimm(mci, i, j, 0);  in igen6_get_dimm_config()
1052 				dtype = get_width(0, mad_dimm);  in igen6_get_dimm_config()
1069 			edac_dbg(0, "MC %d, Channel %d, DIMM %d, Size %llu MiB (%u pages)\n",  in igen6_get_dimm_config()
1081 	edac_dbg(0, "MC %d, total size %llu MiB\n", mc, imc->size >> 20);  in igen6_get_dimm_config()
1083 	return 0;  in igen6_get_dimm_config()
1089 #define TOUUD_OFFSET	0xa8
1095 	edac_dbg(2, "CHANNEL_HASH     : 0x%x\n",  in igen6_reg_dump()
1097 	edac_dbg(2, "CHANNEL_EHASH    : 0x%x\n",  in igen6_reg_dump()
1099 	edac_dbg(2, "MAD_INTER_CHANNEL: 0x%x\n",  in igen6_reg_dump()
1101 	edac_dbg(2, "ECC_ERROR_LOG    : 0x%llx\n",  in igen6_reg_dump()
1104 	for (i = 0; i < NUM_CHANNELS; i++) {  in igen6_reg_dump()
1105 		edac_dbg(2, "MAD_INTRA_CH%d    : 0x%x\n", i,  in igen6_reg_dump()
1107 		edac_dbg(2, "MAD_DIMM_CH%d     : 0x%x\n", i,  in igen6_reg_dump()
1110 	edac_dbg(2, "TOLUD            : 0x%x", igen6_tolud);  in igen6_reg_dump()
1111 	edac_dbg(2, "TOUUD            : 0x%llx", igen6_touud);  in igen6_reg_dump()
1112 	edac_dbg(2, "TOM              : 0x%llx", igen6_tom);  in igen6_reg_dump()
1122 		edac_dbg(0, "Address 0x%llx out of range\n", val);  in debugfs_u64_set()
1123 		return 0;  in debugfs_u64_set()
1126 	pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);  in debugfs_u64_set()
1131 	if (!ecclog_gen_pool_add(0, ecclog))  in debugfs_u64_set()
1134 	return 0;  in debugfs_u64_set()
1209 	return 0;  in igen6_pci_setup()
1231 	return readl(window + MAD_INTER_CHANNEL_OFFSET) == ~0;  in igen6_imc_absent()
1243 	layers[0].type = EDAC_MC_LAYER_CHANNEL;  in igen6_register_mci()
1244 	layers[0].size = NUM_CHANNELS;  in igen6_register_mci()
1245 	layers[0].is_virt_csrow = false;  in igen6_register_mci()
1250 	mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 0);  in igen6_register_mci()
1301 	return 0;  in igen6_register_mci()
1319 	for (i = 0; i < res_cfg->num_imc; i++) {  in igen6_unregister_mcis()
1339 	for (lmc = 0, pmc = 0; pmc < NUM_IMC; pmc++) {  in igen6_register_mcis()
1343 			igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx for mc%d\n", base, pmc);  in igen6_register_mcis()
1374 	return 0;  in igen6_register_mcis()
1387 	struct igen6_imc *imc = &igen6_pvt->imc[0];  in igen6_mem_slice_setup()
1397 	if (imc[0].size < imc[1].size) {  in igen6_mem_slice_setup()
1398 		ms_s_size = imc[0].size;  in igen6_mem_slice_setup()
1402 		ms_l_map  = 0;  in igen6_mem_slice_setup()
1408 	edac_dbg(0, "ms_s_size: %llu MiB, ms_l_map %d\n",  in igen6_mem_slice_setup()
1412 		return 0;  in igen6_mem_slice_setup()
1416 		igen6_printk(KERN_ERR, "Failed to ioremap cmf 0x%llx\n", base);  in igen6_mem_slice_setup()
1423 	edac_dbg(0, "MEM_SLICE_HASH: 0x%llx\n", ms_hash);  in igen6_mem_slice_setup()
1427 	return 0;  in igen6_mem_slice_setup()
1436 		return 0;  in register_err_handler()
1440 				  0, IGEN6_NMI_NAME);  in register_err_handler()
1446 	return 0;  in register_err_handler()
1531 	return 0;  in igen6_probe()
1584 	return 0;  in igen6_init()