19  * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20  * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1  0x0108
64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2  0x010c
65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3  0x0150
66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4  0x0158
67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5  0x015c
68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6  0x0c04
69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7  0x0c08
70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8  0x190F
71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9  0x1918
72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x590f
74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x5918
77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1    0x3e0f
79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2    0x3e18
80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3    0x3e1f
81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4    0x3e30
82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5    0x3e31
83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6    0x3e32
84 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7    0x3e33
85 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8    0x3ec2
86 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9    0x3ec6
87 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10   0x3eca
90 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1	0xa703 /* 8P+8E,  e.g. i7-13700 */
91 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2	0x4640 /* 6P+8E,  e.g. i5-13500, i5-13600, i5-14500 */
92 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3	0x4630 /* 4P+0E,  e.g. i3-13100E */
93 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4	0xa700 /* 8P+16E, e.g. i9-13900, i9-14900 */
94 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5	0xa740 /* 8P+12E, e.g. i7-14700 */
95 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6	0xa704 /* 6P+8E,  e.g. i5-14600 */
98 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1	0xa702 /* 8P+16E, e.g. i9-13950HX */
101 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1	0x4660
102 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_2	0x4668	/* 8P+4E, e.g. i7-12700K */
103 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_3	0x4648	/* 6P+4E, e.g. i5-12600K */
106 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_1	0x4639
107 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_2	0x463c
108 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_3	0x4642
109 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_4	0x4643
110 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_5	0xa731
111 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_6	0xa732
112 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_7	0xa733
113 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_8	0xa741
114 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_9	0xa744
115 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_10	0xa745
122 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
123 #define IE31200_MCHBAR_LOW		0x48
124 #define IE31200_MCHBAR_HIGH		0x4c
130  *  0    Single-bit DRAM ECC Error Flag (DSERR)
132 #define IE31200_ERRSTS			0xc8
134 #define IE31200_ERRSTS_CE		BIT(0)
137 #define IE31200_CAPID0			0xe4
189 	IE31200 = 0,
228 		edac_dbg(0, "In single channel mode\n");  in how_many_channels()
231 		edac_dbg(0, "In dual channel mode\n");  in how_many_channels()
237 		edac_dbg(0, "2 DIMMS per channel disabled\n");  in how_many_channels()
239 		edac_dbg(0, "2 DIMMS per channel enabled\n");  in how_many_channels()
270 			       cfg->reg_eccerrlog_ue_ovfl_mask, 0) < 0)  in ie31200_clear_error_info()
295 		info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
312 	info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
325 		info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
347 			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,  in ie31200_process_error_info()
353 	for (channel = 0; channel < nr_channels; channel++) {  in ie31200_process_error_info()
357 					     info->erraddr >> PAGE_SHIFT, 0, 0,  in ie31200_process_error_info()
363 					     info->erraddr >> PAGE_SHIFT, 0,  in ie31200_process_error_info()
376 	info.erraddr = mce ? mce->addr : 0;  in __ie31200_check()
403 		ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",  in ie31200_map_mchbar()
410 		ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",  in ie31200_map_mchbar()
433 	for (i = 0; i < IE31200_CHANNELS; i++) {  in ie31200_get_dimm_config()
435 		edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);  in ie31200_get_dimm_config()
437 		for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {  in ie31200_get_dimm_config()
439 			edac_dbg(0, "mc: %d, channel: %d, dimm: %d, size: %lld MiB, ranks: %d, DRAM chip type: %d\n",  in ie31200_get_dimm_config()
445 			if (nr_pages == 0)  in ie31200_get_dimm_config()
449 			for (k = 0; k < dimm_info.ranks; k++) {  in ie31200_get_dimm_config()
450 				dimm = edac_get_dimm(mci, (j * dimm_info.ranks) + k, i, 0);  in ie31200_get_dimm_config()
452 				edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);  in ie31200_get_dimm_config()
471 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;  in ie31200_register_mci()
472 	layers[0].size = IE31200_RANKS_PER_CHANNEL;  in ie31200_register_mci()
473 	layers[0].is_virt_csrow = true;  in ie31200_register_mci()
499 	priv->c0errlog = window + cfg->reg_eccerrlog_offset[0];  in ie31200_register_mci()
527 	return 0;  in ie31200_register_mci()
540 	for (i = 0; i < IE31200_IMC_NUM; i++) {  in mce_check()
561 	if ((mce->status & 0xefff) >> 7 != 1)  in mce_handler()
566 	edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n",  in mce_handler()
569 	edac_dbg(0, "TSC 0x%llx\n", mce->tsc);  in mce_handler()
570 	edac_dbg(0, "ADDR 0x%llx\n", mce->addr);  in mce_handler()
571 	edac_dbg(0, "MISC 0x%llx\n", mce->misc);  in mce_handler()
572 	edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n",  in mce_handler()
593 	for (i = 0; i < IE31200_IMC_NUM; i++) {  in ie31200_unregister_mcis()
609 	edac_dbg(0, "MC:\n");  in ie31200_probe1()
616 	for (i = 0; i < cfg->imc_num; i++) {  in ie31200_probe1()
631 	return 0;  in ie31200_probe1()
643 	edac_dbg(0, "MC:\n");  in ie31200_init_one()
644 	if (pci_enable_device(pdev) < 0)  in ie31200_init_one()
647 	if (rc == 0 && !mci_pdev)  in ie31200_init_one()
655 	struct ie31200_priv *priv = ie31200_pvt.priv[0];  in ie31200_remove_one()
657 	edac_dbg(0, "\n");  in ie31200_remove_one()
670 	.reg_eccerrlog_offset[0]	= 0x40c8,
671 	.reg_eccerrlog_offset[1]	= 0x44c8,
672 	.reg_eccerrlog_ce_mask		= BIT_ULL(0),
677 	.reg_mad_dimm_offset[0]		= 0x5004,
678 	.reg_mad_dimm_offset[1]		= 0x5008,
679 	.reg_mad_dimm_size_mask[0]	= GENMASK(7, 0),
681 	.reg_mad_dimm_rank_mask[0]	= BIT(17),
683 	.reg_mad_dimm_width_mask[0]	= BIT(19),
692 	.reg_eccerrlog_offset[0]	= 0x4048,
693 	.reg_eccerrlog_offset[1]	= 0x4448,
694 	.reg_eccerrlog_ce_mask		= BIT_ULL(0),
699 	.reg_mad_dimm_offset[0]		= 0x500c,
700 	.reg_mad_dimm_offset[1]		= 0x5010,
701 	.reg_mad_dimm_size_mask[0]	= GENMASK(5, 0),
703 	.reg_mad_dimm_rank_mask[0]	= BIT(10),
705 	.reg_mad_dimm_width_mask[0]	= GENMASK(9, 8),
715 	.reg_eccerrlog_offset[0]	= 0xe048,
716 	.reg_eccerrlog_offset[1]	= 0xe848,
717 	.reg_eccerrlog_ce_mask		= BIT_ULL(0),
723 	.msr_clear_eccerrlog_offset	= 0x791,
724 	.reg_mad_dimm_offset[0]		= 0xd80c,
725 	.reg_mad_dimm_offset[1]		= 0xd810,
727 	.reg_mad_dimm_size_mask[0]	= GENMASK(6, 0),
729 	.reg_mad_dimm_rank_mask[0]	= GENMASK(10, 9),
731 	.reg_mad_dimm_width_mask[0]	= GENMASK(8, 7),
778 	{ 0, } /* 0 terminated list. */
796 	if (pci_rc < 0)  in ie31200_init()
800 		ie31200_registered = 0;  in ie31200_init()
801 		for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {  in ie31200_init()
810 			edac_dbg(0, "ie31200 pci_get_device fail\n");  in ie31200_init()
816 		if (pci_rc < 0) {  in ie31200_init()
817 			edac_dbg(0, "ie31200 init fail\n");  in ie31200_init()
823 	return 0;  in ie31200_init()