Lines Matching full:row
116 #define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8)
134 #define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8)
138 * 6:4 row attr of odd rank, i.e. 1
140 * 2:0 row attr of even rank, i.e. 0
280 int row, chan; in i82975x_process_error_info() local
300 row = edac_mc_find_csrow_by_page(mci, page); in i82975x_process_error_info()
302 if (row == -1) { in i82975x_process_error_info()
310 chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1; in i82975x_process_error_info()
313 (1 << mci->csrows[row]->channels[chan]->dimm->grain)); in i82975x_process_error_info()
318 row, -1, -1, in i82975x_process_error_info()
323 row, chan ? chan : 0, -1, in i82975x_process_error_info()
349 int row; in dual_channel_active() local
352 for (dualch = 1, row = 0; dualch && (row < 4); row++) { in dual_channel_active()
353 drb[row][0] = readb(mch_window + I82975X_DRB + row); in dual_channel_active()
354 drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80); in dual_channel_active()
355 dualch = dualch && (drb[row][0] == drb[row][1]); in dual_channel_active()
374 * The dram row boundary (DRB) reg values are boundary address in i82975x_init_csrows()
375 * for each DRAM row with a granularity of 32 or 64MB (single/dual in i82975x_init_csrows()