Lines Matching full:dram
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
44 * 7:0 DRAM ECC Syndrome
47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
58 * 9 non-DRAM lock error (ndlock)
61 * 1 ECC UE (multibit DRAM error)
62 * 0 ECC CE (singlebit DRAM error)
76 * 9 non-DRAM lock error (ndlock)
79 * 1 ECC UE (multibit DRAM error)
80 * 0 ECC CE (singlebit DRAM error)
86 * 1 ECC UE (multibit DRAM error)
87 * 0 ECC CE (singlebit DRAM error)
93 * 1 ECC UE (multibit DRAM error)
94 * 0 ECC CE (singlebit DRAM error)
97 #define I82975X_XEAP 0xfc /* Extended Dram Error Address Pointer (8b)
100 * 0 Bit32 of the Dram Error Address
116 #define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8)
134 #define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8)
171 #define I82975X_DRC 0x120 /* DRAM Controller Mode0 (32b)
187 * 1:0 DRAM type 10=Second Revision
195 #define I82975X_DRC_M1 0x124 /* DRAM Controller Mode1 (32b)
374 * The dram row boundary (DRB) reg values are boundary address in i82975x_init_csrows()
375 * for each DRAM row with a granularity of 32 or 64MB (single/dual in i82975x_init_csrows()
401 * Initialise dram labels in i82975x_init_csrows()
445 i82975x_printk(KERN_INFO, "DRAM Timings : Ch0 Ch1\n" in i82975x_print_dram_timings()