28 #define PCI_DEVICE_ID_INTEL_82975_0	0x277c
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP		0x58	/* Dram Error Address Pointer (32b)
39 					 * 0     0: CH0; 1: CH1
42 #define I82975X_DERRSYN		0x5c	/* Dram Error SYNdrome (8b)
44 					 *  7:0  DRAM ECC Syndrome
47 #define I82975X_DES		0x5d	/* Dram ERRor DeSTination (8b)
48 					 * 0h:    Processor Memory Reads
53 #define I82975X_ERRSTS		0xc8	/* Error Status Register (16b)
62 					 *  0    ECC CE (singlebit DRAM error)
71 #define I82975X_ERRCMD		0xca	/* Error Command (16b)
80 					 *  0    ECC CE (singlebit DRAM error)
83 #define I82975X_SMICMD		0xcc	/* Error Command (16b)
87 					 *  0    ECC CE (singlebit DRAM error)
90 #define I82975X_SCICMD		0xce	/* Error Command (16b)
94 					 *  0    ECC CE (singlebit DRAM error)
97 #define I82975X_XEAP	0xfc	/* Extended Dram Error Address Pointer (8b)
100 					 * 0     Bit32 of the Dram Error Address
103 #define I82975X_MCHBAR		0x44	/*
108 					 *  0    mem-mapped config space enable
116 #define I82975X_DRB		0x100	/* DRAM Row Boundary (8b x 8)
122 					 * 1:0 set to 0
124 #define I82975X_DRB_CH0R0		0x100
125 #define I82975X_DRB_CH0R1		0x101
126 #define I82975X_DRB_CH0R2		0x102
127 #define I82975X_DRB_CH0R3		0x103
128 #define I82975X_DRB_CH1R0		0x180
129 #define I82975X_DRB_CH1R1		0x181
130 #define I82975X_DRB_CH1R2		0x182
131 #define I82975X_DRB_CH1R3		0x183
134 #define I82975X_DRA		0x108	/* DRAM Row Attribute (4b x 8)
140 					 *  2:0  row attr of even rank, i.e. 0
149 #define I82975X_DRA_CH0R01		0x108
150 #define I82975X_DRA_CH0R23		0x109
151 #define I82975X_DRA_CH1R01		0x188
152 #define I82975X_DRA_CH1R23		0x189
155 #define I82975X_BNKARC	0x10e /* Type of device in each rank - Bank Arch (16b)
161 					 * 1:0  Rank 0 architecture
166 #define I82975X_C0BNKARC	0x10e
167 #define I82975X_C1BNKARC	0x18e
171 #define I82975X_DRC		0x120 /* DRAM Controller Mode0 (32b)
187 					 *  1:0  DRAM type 10=Second Revision
191 #define I82975X_DRC_CH0M0		0x120
192 #define I82975X_DRC_CH1M0		0x1A0
195 #define I82975X_DRC_M1	0x124 /* DRAM Controller Mode1 (32b)
196 					 * 31	0=Standard Address Map
198 					 * 30:0	reserved
201 #define I82975X_DRC_CH0M1		0x124
202 #define I82975X_DRC_CH1M1		0x1A4
205 	I82975X = 0,
222 	u8 chan;		/* the channel is bit 0 of EAP */
257 	pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);  in i82975x_get_error_info()
265 	if (!(info->errsts2 & 0x0003))  in i82975x_get_error_info()
268 	if ((info->errsts ^ info->errsts2) & 0x0003) {  in i82975x_get_error_info()
283 	if (!(info->errsts2 & 0x0003))  in i82975x_process_error_info()
284 		return 0;  in i82975x_process_error_info()
289 	if ((info->errsts ^ info->errsts2) & 0x0003) {  in i82975x_process_error_info()
290 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,  in i82975x_process_error_info()
298 		page |= 0x80000000;  in i82975x_process_error_info()
305 			"\t EAP=0x%08x\n"  in i82975x_process_error_info()
306 			"\tPAGE=0x%08x\n",  in i82975x_process_error_info()
307 			(info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);  in i82975x_process_error_info()
308 		return 0;  in i82975x_process_error_info()
310 	chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1;  in i82975x_process_error_info()
315 	if (info->errsts & 0x0002)  in i82975x_process_error_info()
317 				     page, offst, 0,  in i82975x_process_error_info()
323 				     row, chan ? chan : 0, -1,  in i82975x_process_error_info()
337 /* Return 1 if dual channel mode is active.  Else return 0. */
342 	 * bit-0 giving the channel of the error location.  in dual_channel_active()
345 	 * bit-0 will resolve ok in symmetric area of mixed  in dual_channel_active()
352 	for (dualch = 1, row = 0; dualch && (row < 4); row++) {  in dual_channel_active()
353 		drb[row][0] = readb(mch_window + I82975X_DRB + row);  in dual_channel_active()
354 		drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);  in dual_channel_active()
355 		dualch = dualch && (drb[row][0] == drb[row][1]);  in dual_channel_active()
370 	last_cumul_size = 0;  in i82975x_init_csrows()
381 	for (index = 0; index < mci->nr_csrows; index++) {  in i82975x_init_csrows()
385 					((index >= 4) ? 0x80 : 0));  in i82975x_init_csrows()
394 		edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);  in i82975x_init_csrows()
403 		 *   [0-7] for single-channel; i.e. csrow->nr_channels = 1  in i82975x_init_csrows()
404 		 *   [0-3] for dual-channel; i.e. csrow->nr_channels = 2  in i82975x_init_csrows()
406 		for (chan = 0; chan < csrow->nr_channels; chan++) {  in i82975x_init_csrows()
412 				 (chan == 0) ? 'A' : 'B',  in i82975x_init_csrows()
443 	dtreg[0] = readl(mch_window + 0x114);  in i82975x_print_dram_timings()
444 	dtreg[1] = readl(mch_window + 0x194);  in i82975x_print_dram_timings()
450 		(dtreg[0] >> 19 ) & 0x0f,  in i82975x_print_dram_timings()
451 			(dtreg[1] >> 19) & 0x0f,  in i82975x_print_dram_timings()
452 		caslats[(dtreg[0] >> 8) & 0x03],  in i82975x_print_dram_timings()
453 			caslats[(dtreg[1] >> 8) & 0x03],  in i82975x_print_dram_timings()
454 		((dtreg[0] >> 4) & 0x07) + 2,  in i82975x_print_dram_timings()
455 			((dtreg[1] >> 4) & 0x07) + 2,  in i82975x_print_dram_timings()
456 		(dtreg[0] & 0x07) + 2,  in i82975x_print_dram_timings()
457 			(dtreg[1] & 0x07) + 2  in i82975x_print_dram_timings()
479 	edac_dbg(0, "\n");  in i82975x_probe1()
486 	mchbar &= 0xffffc000;	/* bits 31:14 used for 16K window */  in i82975x_probe1()
487 	mch_window = ioremap(mchbar, 0x1000);  in i82975x_probe1()
494 	i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",  in i82975x_probe1()
497 	c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);  in i82975x_probe1()
501 	c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);  in i82975x_probe1()
505 	i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);  in i82975x_probe1()
506 	i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);  in i82975x_probe1()
507 	i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);  in i82975x_probe1()
508 	i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);  in i82975x_probe1()
509 	i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);  in i82975x_probe1()
510 	i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);  in i82975x_probe1()
511 	i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);  in i82975x_probe1()
512 	i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);  in i82975x_probe1()
515 	drc[0] = readl(mch_window + I82975X_DRC_CH0M0);  in i82975x_probe1()
518 	i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],  in i82975x_probe1()
519 			((drc[0] >> 21) & 3) == 1 ?  in i82975x_probe1()
521 	i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],  in i82975x_probe1()
525 	i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",  in i82975x_probe1()
527 	i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",  in i82975x_probe1()
532 	if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {  in i82975x_probe1()
539 	/* assuming only one controller, index thus is 0 */  in i82975x_probe1()
540 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;  in i82975x_probe1()
541 	layers[0].size = I82975X_NR_DIMMS;  in i82975x_probe1()
542 	layers[0].is_virt_csrow = true;  in i82975x_probe1()
546 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));  in i82975x_probe1()
577 	return 0;  in i82975x_probe1()
588 /* returns count (>= 0), or negative on error */
594 	edac_dbg(0, "\n");  in i82975x_init_one()
596 	if (pci_enable_device(pdev) < 0)  in i82975x_init_one()
612 	edac_dbg(0, "\n");  in i82975x_remove_one()
627 		PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
631 		0,
632 	}	/* 0 terminated list. */
654 	if (pci_rc < 0)  in i82975x_init()
662 			edac_dbg(0, "i82975x pci_get_device fail\n");  in i82975x_init()
669 		if (pci_rc < 0) {  in i82975x_init()
670 			edac_dbg(0, "i82975x init fail\n");  in i82975x_init()
676 	return 0;  in i82975x_init()
706 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");