Lines Matching +full:ras +full:- +full:to +full:- +full:cas
18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
23 * 4 dimm's, each with up to 8GB.
83 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
88 /* Non-fatal error register */
140 * Error masks are according with Table 5-17 of i5400 datasheet
144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
150 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
152 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
154 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
155 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
157 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
158 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
159 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
160 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
162 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
164 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
166 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
171 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
172 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
176 * Names to translate bit error into something useful
179 [0] = "Memory Write error on non-redundant retry",
180 [1] = "Memory or FB-DIMM configuration CRC read error",
183 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
185 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
187 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
189 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
190 [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
192 [13] = "FB-DIMM Configuration Write error on first attempt",
193 [14] = "Memory or FB-DIMM configuration CRC read error",
194 [15] = "Channel Failed-Over Occurred",
195 [16] = "Correctable Non-Mirrored Demand Data ECC",
197 [18] = "Correctable Resilver- or Spare-Copy Data ECC",
199 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
201 [22] = "Non-Redundant Fast Reset Timeout",
206 [27] = "DIMM-Spare Copy Completed",
207 [28] = "DIMM-Isolation Completed",
244 /* mask to all non-fatal errors */
262 /* masks for non-fatal error register */
271 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */ in from_nf_ferr()
283 * Defines to extract the various fields from the
284 * MTRx - Memory Technology Registers
298 /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */
362 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
363 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
370 /* These registers are input ONLY if there was a Non-Rec Error */
371 u16 nrecmema; /* Non-Recoverable Mem log A */
372 u32 nrecmemb; /* Non-Recoverable Mem log B */
376 /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
377 5400 better to use an inline function than a macro in this case */
380 return ((info->nrecmema) >> 12) & 0x7; in nrec_bank()
384 return ((info->nrecmema) >> 8) & 0xf; in nrec_rank()
388 return ((info->nrecmema)) & 0xff; in nrec_buf_id()
392 return (info->nrecmemb) >> 31; in nrec_rdwr()
394 /* This applies to both NREC and REC string so it can be used with nrec_rdwr
402 return ((info->nrecmemb) >> 16) & 0x1fff; in nrec_cas()
406 return (info->nrecmemb) & 0xffff; in nrec_ras()
410 return ((info->recmema) >> 12) & 0x7; in rec_bank()
414 return ((info->recmema) >> 8) & 0xf; in rec_rank()
418 return (info->recmemb) >> 31; in rec_rdwr()
422 return ((info->recmemb) >> 16) & 0x1fff; in rec_cas()
426 return (info->recmemb) & 0xffff; in rec_ras()
442 pvt = mci->pvt_info; in i5400_get_error_info()
445 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); in i5400_get_error_info()
455 info->ferr_fat_fbd = value; in i5400_get_error_info()
458 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
459 NERR_FAT_FBD, &info->nerr_fat_fbd); in i5400_get_error_info()
460 pci_read_config_word(pvt->branchmap_werrors, in i5400_get_error_info()
461 NRECMEMA, &info->nrecmema); in i5400_get_error_info()
462 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
463 NRECMEMB, &info->nrecmemb); in i5400_get_error_info()
466 pci_write_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
469 info->ferr_fat_fbd = 0; in i5400_get_error_info()
470 info->nerr_fat_fbd = 0; in i5400_get_error_info()
471 info->nrecmema = 0; in i5400_get_error_info()
472 info->nrecmemb = 0; in i5400_get_error_info()
475 /* read in the 1st NON-FATAL error register */ in i5400_get_error_info()
476 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); in i5400_get_error_info()
478 /* If there is an error, then read in the 1st NON-FATAL error in i5400_get_error_info()
481 info->ferr_nf_fbd = value; in i5400_get_error_info()
484 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
485 NERR_NF_FBD, &info->nerr_nf_fbd); in i5400_get_error_info()
486 pci_read_config_word(pvt->branchmap_werrors, in i5400_get_error_info()
487 RECMEMA, &info->recmema); in i5400_get_error_info()
488 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
489 RECMEMB, &info->recmemb); in i5400_get_error_info()
490 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
491 REDMEMB, &info->redmemb); in i5400_get_error_info()
494 pci_write_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
497 info->ferr_nf_fbd = 0; in i5400_get_error_info()
498 info->nerr_nf_fbd = 0; in i5400_get_error_info()
499 info->recmema = 0; in i5400_get_error_info()
500 info->recmemb = 0; in i5400_get_error_info()
501 info->redmemb = 0; in i5400_get_error_info()
523 int ras, cas; in i5400_proccess_non_recoverable_info() local
535 type = "NON-FATAL uncorrected"; in i5400_proccess_non_recoverable_info()
537 type = "NON-FATAL recoverable"; in i5400_proccess_non_recoverable_info()
541 branch = extract_fbdchan_indx(info->ferr_fat_fbd); in i5400_proccess_non_recoverable_info()
544 /* Use the NON-Recoverable macros to extract data */ in i5400_proccess_non_recoverable_info()
549 ras = nrec_ras(info); in i5400_proccess_non_recoverable_info()
550 cas = nrec_cas(info); in i5400_proccess_non_recoverable_info()
552 …s DIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n", in i5400_proccess_non_recoverable_info()
554 buf_id, rdwr_str(rdwr), ras, cas); in i5400_proccess_non_recoverable_info()
561 "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)", in i5400_proccess_non_recoverable_info()
562 bank, buf_id, ras, cas, allErrors, error_name[errnum]); in i5400_proccess_non_recoverable_info()
565 branch >> 1, -1, rank, in i5400_proccess_non_recoverable_info()
575 * handle the Intel NON-FATAL errors, if any
587 int ras, cas; in i5400_process_nonfatal_error_info() local
591 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK); in i5400_process_nonfatal_error_info()
606 branch = extract_fbdchan_indx(info->ferr_nf_fbd); in i5400_process_nonfatal_error_info()
609 if (REC_ECC_LOCATOR_ODD(info->redmemb)) in i5400_process_nonfatal_error_info()
612 /* Convert channel to be based from zero, instead of in i5400_process_nonfatal_error_info()
619 ras = rec_ras(info); in i5400_process_nonfatal_error_info()
620 cas = rec_cas(info); in i5400_process_nonfatal_error_info()
625 edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", in i5400_process_nonfatal_error_info()
627 rdwr_str(rdwr), ras, cas); in i5400_process_nonfatal_error_info()
631 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s " in i5400_process_nonfatal_error_info()
632 "RAS=%d CAS=%d, CE Err=0x%lx (%s))", in i5400_process_nonfatal_error_info()
633 branch >> 1, bank, rdwr_str(rdwr), ras, cas, in i5400_process_nonfatal_error_info()
647 branch = extract_fbdchan_indx(info->ferr_nf_fbd); in i5400_process_nonfatal_error_info()
650 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))", in i5400_process_nonfatal_error_info()
663 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); in i5400_process_error_info()
666 /* now handle any non-fatal errors that occurred */ in i5400_process_error_info()
703 pvt = mci->pvt_info; in i5400_put_devices()
706 pci_dev_put(pvt->branch_1); in i5400_put_devices()
707 pci_dev_put(pvt->branch_0); in i5400_put_devices()
708 pci_dev_put(pvt->fsb_error_regs); in i5400_put_devices()
709 pci_dev_put(pvt->branchmap_werrors); in i5400_put_devices()
714 * device/functions we want to reference for this driver
716 * Need to 'get' device 16 func 1 and func 2
723 pvt = mci->pvt_info; in i5400_get_devices()
724 pvt->branchmap_werrors = NULL; in i5400_get_devices()
725 pvt->fsb_error_regs = NULL; in i5400_get_devices()
726 pvt->branch_0 = NULL; in i5400_get_devices()
727 pvt->branch_1 = NULL; in i5400_get_devices()
729 /* Attempt to 'get' the MCH register we want */ in i5400_get_devices()
743 return -ENODEV; in i5400_get_devices()
747 if (PCI_FUNC(pdev->devfn) == 1) in i5400_get_devices()
750 pvt->branchmap_werrors = pdev; in i5400_get_devices()
766 pci_dev_put(pvt->branchmap_werrors); in i5400_get_devices()
767 return -ENODEV; in i5400_get_devices()
771 if (PCI_FUNC(pdev->devfn) == 2) in i5400_get_devices()
774 pvt->fsb_error_regs = pdev; in i5400_get_devices()
776 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n", in i5400_get_devices()
777 pci_name(pvt->system_address), in i5400_get_devices()
778 pvt->system_address->vendor, pvt->system_address->device); in i5400_get_devices()
779 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", in i5400_get_devices()
780 pci_name(pvt->branchmap_werrors), in i5400_get_devices()
781 pvt->branchmap_werrors->vendor, in i5400_get_devices()
782 pvt->branchmap_werrors->device); in i5400_get_devices()
783 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n", in i5400_get_devices()
784 pci_name(pvt->fsb_error_regs), in i5400_get_devices()
785 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); in i5400_get_devices()
787 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, in i5400_get_devices()
789 if (!pvt->branch_0) { in i5400_get_devices()
795 pci_dev_put(pvt->fsb_error_regs); in i5400_get_devices()
796 pci_dev_put(pvt->branchmap_werrors); in i5400_get_devices()
797 return -ENODEV; in i5400_get_devices()
800 /* If this device claims to have more than 2 channels then in i5400_get_devices()
803 if (pvt->maxch < CHANNELS_PER_BRANCH) in i5400_get_devices()
806 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL, in i5400_get_devices()
808 if (!pvt->branch_1) { in i5400_get_devices()
816 pci_dev_put(pvt->branch_0); in i5400_get_devices()
817 pci_dev_put(pvt->fsb_error_regs); in i5400_get_devices()
818 pci_dev_put(pvt->branchmap_werrors); in i5400_get_devices()
819 return -ENODEV; in i5400_get_devices()
844 amb_present = pvt->b0_ambpresent1; in determine_amb_present_reg()
846 amb_present = pvt->b0_ambpresent0; in determine_amb_present_reg()
849 amb_present = pvt->b1_ambpresent1; in determine_amb_present_reg()
851 amb_present = pvt->b1_ambpresent0; in determine_amb_present_reg()
867 /* There is one MTR for each slot pair of FB-DIMMs, in determine_mtr()
873 edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n", in determine_mtr()
879 mtr = pvt->b0_mtr[n]; in determine_mtr()
881 mtr = pvt->b1_mtr[n]; in determine_mtr()
908 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : in decode_mtr()
909 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : in decode_mtr()
910 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : in decode_mtr()
911 "65,536 - 16 rows"); in decode_mtr()
913 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : in decode_mtr()
914 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : in decode_mtr()
915 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : in decode_mtr()
943 addrBits -= 20; /* divide by 2^^20 */ in handle_channel()
944 addrBits -= 3; /* 8 bits per bytes */ in handle_channel()
946 dinfo->megabytes = 1 << addrBits; in handle_channel()
976 * Start with the highest dimm first, to display it first in calculate_dimm_size()
979 max_dimms = pvt->maxdimmperch; in calculate_dimm_size()
980 for (dimm = max_dimms - 1; dimm >= 0; dimm--) { in calculate_dimm_size()
985 n = snprintf(p, space, "---------------------------" in calculate_dimm_size()
986 "-------------------------------"); in calculate_dimm_size()
988 space -= n; in calculate_dimm_size()
995 space -= n; in calculate_dimm_size()
997 for (channel = 0; channel < pvt->maxch; channel++) { in calculate_dimm_size()
998 dinfo = &pvt->dimm_info[dimm][channel]; in calculate_dimm_size()
1000 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); in calculate_dimm_size()
1002 space -= n; in calculate_dimm_size()
1010 n = snprintf(p, space, "---------------------------" in calculate_dimm_size()
1011 "-------------------------------"); in calculate_dimm_size()
1013 space -= n; in calculate_dimm_size()
1021 space -= n; in calculate_dimm_size()
1022 for (channel = 0; channel < pvt->maxch; channel++) { in calculate_dimm_size()
1025 space -= n; in calculate_dimm_size()
1028 space -= n; in calculate_dimm_size()
1038 space -= n; in calculate_dimm_size()
1060 pvt = mci->pvt_info; in i5400_get_mc_regs()
1062 pci_read_config_dword(pvt->system_address, AMBASE, in i5400_get_mc_regs()
1063 &pvt->u.ambase_bottom); in i5400_get_mc_regs()
1064 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), in i5400_get_mc_regs()
1065 &pvt->u.ambase_top); in i5400_get_mc_regs()
1067 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", in i5400_get_mc_regs()
1068 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); in i5400_get_mc_regs()
1071 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); in i5400_get_mc_regs()
1072 pvt->tolm >>= 12; in i5400_get_mc_regs()
1074 pvt->tolm, pvt->tolm); in i5400_get_mc_regs()
1076 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); in i5400_get_mc_regs()
1078 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); in i5400_get_mc_regs()
1080 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); in i5400_get_mc_regs()
1081 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); in i5400_get_mc_regs()
1083 /* Get the MIR[0-1] regs */ in i5400_get_mc_regs()
1084 limit = (pvt->mir0 >> 4) & 0x0fff; in i5400_get_mc_regs()
1085 way0 = pvt->mir0 & 0x1; in i5400_get_mc_regs()
1086 way1 = pvt->mir0 & 0x2; in i5400_get_mc_regs()
1089 limit = (pvt->mir1 >> 4) & 0xfff; in i5400_get_mc_regs()
1090 way0 = pvt->mir1 & 0x1; in i5400_get_mc_regs()
1091 way1 = pvt->mir1 & 0x2; in i5400_get_mc_regs()
1095 /* Get the set of MTR[0-3] regs by each branch */ in i5400_get_mc_regs()
1100 pci_read_config_word(pvt->branch_0, where, in i5400_get_mc_regs()
1101 &pvt->b0_mtr[slot_row]); in i5400_get_mc_regs()
1104 slot_row, where, pvt->b0_mtr[slot_row]); in i5400_get_mc_regs()
1106 if (pvt->maxch < CHANNELS_PER_BRANCH) { in i5400_get_mc_regs()
1107 pvt->b1_mtr[slot_row] = 0; in i5400_get_mc_regs()
1112 pci_read_config_word(pvt->branch_1, where, in i5400_get_mc_regs()
1113 &pvt->b1_mtr[slot_row]); in i5400_get_mc_regs()
1115 slot_row, where, pvt->b1_mtr[slot_row]); in i5400_get_mc_regs()
1122 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); in i5400_get_mc_regs()
1124 pci_read_config_word(pvt->branch_0, AMBPRESENT_0, in i5400_get_mc_regs()
1125 &pvt->b0_ambpresent0); in i5400_get_mc_regs()
1126 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); in i5400_get_mc_regs()
1127 pci_read_config_word(pvt->branch_0, AMBPRESENT_1, in i5400_get_mc_regs()
1128 &pvt->b0_ambpresent1); in i5400_get_mc_regs()
1129 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); in i5400_get_mc_regs()
1132 if (pvt->maxch < CHANNELS_PER_BRANCH) { in i5400_get_mc_regs()
1133 pvt->b1_ambpresent0 = 0; in i5400_get_mc_regs()
1134 pvt->b1_ambpresent1 = 0; in i5400_get_mc_regs()
1139 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); in i5400_get_mc_regs()
1141 pci_read_config_word(pvt->branch_1, AMBPRESENT_0, in i5400_get_mc_regs()
1142 &pvt->b1_ambpresent0); in i5400_get_mc_regs()
1143 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n", in i5400_get_mc_regs()
1144 pvt->b1_ambpresent0); in i5400_get_mc_regs()
1145 pci_read_config_word(pvt->branch_1, AMBPRESENT_1, in i5400_get_mc_regs()
1146 &pvt->b1_ambpresent1); in i5400_get_mc_regs()
1147 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n", in i5400_get_mc_regs()
1148 pvt->b1_ambpresent1); in i5400_get_mc_regs()
1174 pvt = mci->pvt_info; in i5400_init_dimms()
1179 * FIXME: remove pvt->dimm_info[slot][channel] and use the 3 in i5400_init_dimms()
1182 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; in i5400_init_dimms()
1184 for (slot = 0; slot < mci->layers[2].size; slot++) { in i5400_init_dimms()
1193 size_mb = pvt->dimm_info[slot][channel].megabytes; in i5400_init_dimms()
1199 dimm->nr_pages = size_mb << 8; in i5400_init_dimms()
1200 dimm->grain = 8; in i5400_init_dimms()
1201 dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ? in i5400_init_dimms()
1203 dimm->mtype = MEM_FB_DDR2; in i5400_init_dimms()
1206 * is similar to Chipkill. in i5400_init_dimms()
1208 dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ? in i5400_init_dimms()
1216 * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+. in i5400_init_dimms()
1219 mci->dimms[0]->edac_mode = EDAC_SECDED; in i5400_init_dimms()
1233 pvt = mci->pvt_info; in i5400_enable_error_reporting()
1236 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, in i5400_enable_error_reporting()
1242 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, in i5400_enable_error_reporting()
1247 * i5400_probe1 Probe for ONE instance of device to see if it is
1260 return -EINVAL; in i5400_probe1()
1263 pdev->bus->number, in i5400_probe1()
1264 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); in i5400_probe1()
1267 if (PCI_FUNC(pdev->devfn) != 0) in i5400_probe1()
1268 return -ENODEV; in i5400_probe1()
1286 return -ENOMEM; in i5400_probe1()
1290 mci->pdev = &pdev->dev; /* record ptr to the generic device */ in i5400_probe1()
1292 pvt = mci->pvt_info; in i5400_probe1()
1293 pvt->system_address = pdev; /* Record this device in our private */ in i5400_probe1()
1294 pvt->maxch = MAX_CHANNELS; in i5400_probe1()
1295 pvt->maxdimmperch = DIMMS_PER_CHANNEL; in i5400_probe1()
1297 /* 'get' the pci devices we want to reserve for our use */ in i5400_probe1()
1301 /* Time to get serious */ in i5400_probe1()
1304 mci->mc_idx = 0; in i5400_probe1()
1305 mci->mtype_cap = MEM_FLAG_FB_DDR2; in i5400_probe1()
1306 mci->edac_ctl_cap = EDAC_FLAG_NONE; in i5400_probe1()
1307 mci->edac_cap = EDAC_FLAG_NONE; in i5400_probe1()
1308 mci->mod_name = "i5400_edac.c"; in i5400_probe1()
1309 mci->ctl_name = i5400_devs[dev_idx].ctl_name; in i5400_probe1()
1310 mci->dev_name = pci_name(pdev); in i5400_probe1()
1311 mci->ctl_page_to_phys = NULL; in i5400_probe1()
1313 /* Set the function pointer to an actual operation function */ in i5400_probe1()
1314 mci->edac_check = i5400_check_error; in i5400_probe1()
1319 …edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonze… in i5400_probe1()
1320 mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */ in i5400_probe1()
1326 /* add this new MC control structure to EDAC's list of MCs */ in i5400_probe1()
1338 i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); in i5400_probe1()
1341 "%s(): Unable to create PCI control\n", in i5400_probe1()
1357 return -ENODEV; in i5400_probe1()
1379 return i5400_probe1(pdev, id->driver_data); in i5400_init_one()
1395 mci = edac_mc_del_mc(&pdev->dev); in i5400_remove_one()
1399 /* retrieve references to resources, and free those resources */ in i5400_remove_one()
1432 * Try to initialize this module for its devices
1465 MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - "