Lines Matching full:pvt
388 struct i5000_pvt *pvt;
391 pvt = mci->pvt_info;
394 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
406 pci_read_config_dword(pvt->branchmap_werrors,
408 pci_read_config_word(pvt->branchmap_werrors,
410 pci_read_config_dword(pvt->branchmap_werrors,
414 pci_write_config_dword(pvt->branchmap_werrors,
424 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
432 pci_read_config_dword(pvt->branchmap_werrors,
434 pci_read_config_word(pvt->branchmap_werrors,
436 pci_read_config_dword(pvt->branchmap_werrors,
438 pci_read_config_dword(pvt->branchmap_werrors,
442 pci_write_config_dword(pvt->branchmap_werrors,
782 struct i5000_pvt *pvt;
785 pvt = mci->pvt_info;
811 pvt->branchmap_werrors = pdev;
828 pci_dev_put(pvt->branchmap_werrors);
837 pvt->fsb_error_regs = pdev;
840 pci_name(pvt->system_address),
841 pvt->system_address->vendor, pvt->system_address->device);
843 pci_name(pvt->branchmap_werrors),
844 pvt->branchmap_werrors->vendor,
845 pvt->branchmap_werrors->device);
847 pci_name(pvt->fsb_error_regs),
848 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
860 pci_dev_put(pvt->branchmap_werrors);
861 pci_dev_put(pvt->fsb_error_regs);
865 pvt->branch_0 = pdev;
870 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
883 pci_dev_put(pvt->branchmap_werrors);
884 pci_dev_put(pvt->fsb_error_regs);
885 pci_dev_put(pvt->branch_0);
889 pvt->branch_1 = pdev;
901 struct i5000_pvt *pvt;
903 pvt = mci->pvt_info;
905 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
906 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
907 pci_dev_put(pvt->branch_0); /* DEV 21 */
910 if (pvt->maxch >= CHANNELS_PER_BRANCH)
911 pci_dev_put(pvt->branch_1); /* DEV 22 */
927 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
933 amb_present = pvt->b0_ambpresent1;
935 amb_present = pvt->b0_ambpresent0;
938 amb_present = pvt->b1_ambpresent1;
940 amb_present = pvt->b1_ambpresent0;
947 * determine_mtr(pvt, csrow, channel)
951 static int determine_mtr(struct i5000_pvt *pvt, int slot, int channel)
956 mtr = pvt->b0_mtr[slot];
958 mtr = pvt->b1_mtr[slot];
992 static void handle_channel(struct i5000_pvt *pvt, int slot, int channel,
999 mtr = determine_mtr(pvt, slot, channel);
1001 amb_present_reg = determine_amb_present_reg(pvt, channel);
1034 static void calculate_dimm_size(struct i5000_pvt *pvt)
1055 for (slot = pvt->maxdimmperch - 1; slot >= 0; slot--) {
1072 for (channel = 0; channel < pvt->maxch; channel++) {
1073 dinfo = &pvt->dimm_info[slot][channel];
1074 handle_channel(pvt, slot, channel, dinfo);
1103 for (channel = 0; channel < pvt->maxch; channel++) {
1133 struct i5000_pvt *pvt;
1139 pvt = mci->pvt_info;
1141 pci_read_config_dword(pvt->system_address, AMBASE,
1142 &pvt->u.ambase_bottom);
1143 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1144 &pvt->u.ambase_top);
1147 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1150 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1151 pvt->tolm >>= 12;
1153 pvt->tolm, pvt->tolm);
1155 actual_tolm = pvt->tolm << 28;
1159 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1160 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1161 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1164 limit = (pvt->mir0 >> 4) & 0x0FFF;
1165 way0 = pvt->mir0 & 0x1;
1166 way1 = pvt->mir0 & 0x2;
1169 limit = (pvt->mir1 >> 4) & 0x0FFF;
1170 way0 = pvt->mir1 & 0x1;
1171 way1 = pvt->mir1 & 0x2;
1174 limit = (pvt->mir2 >> 4) & 0x0FFF;
1175 way0 = pvt->mir2 & 0x1;
1176 way1 = pvt->mir2 & 0x2;
1184 pci_read_config_word(pvt->branch_0, where,
1185 &pvt->b0_mtr[slot_row]);
1188 slot_row, where, pvt->b0_mtr[slot_row]);
1190 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1191 pci_read_config_word(pvt->branch_1, where,
1192 &pvt->b1_mtr[slot_row]);
1194 slot_row, where, pvt->b1_mtr[slot_row]);
1196 pvt->b1_mtr[slot_row] = 0;
1204 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1206 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1207 &pvt->b0_ambpresent0);
1208 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1209 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1210 &pvt->b0_ambpresent1);
1211 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1214 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1215 pvt->b1_ambpresent0 = 0;
1216 pvt->b1_ambpresent1 = 0;
1221 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1223 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1224 &pvt->b1_ambpresent0);
1226 pvt->b1_ambpresent0);
1227 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1228 &pvt->b1_ambpresent1);
1230 pvt->b1_ambpresent1);
1235 calculate_dimm_size(pvt);
1249 struct i5000_pvt *pvt;
1258 pvt = mci->pvt_info;
1259 max_csrows = pvt->maxdimmperch * 2;
1271 for (channel = 0; channel < pvt->maxch; channel++) {
1273 mtr = determine_mtr(pvt, slot, channel);
1281 csrow_megs = pvt->dimm_info[slot][channel].megabytes;
1309 struct i5000_pvt *pvt;
1312 pvt = mci->pvt_info;
1315 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1321 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1358 struct i5000_pvt *pvt;
1400 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1408 pvt = mci->pvt_info;
1409 pvt->system_address = pdev; /* Record this device in our private */
1410 pvt->maxch = num_channels;
1411 pvt->maxdimmperch = num_dimms_per_channel;