3  * Copyright (C) 2008-2009 Akamai Technologies, Inc.
18 #include <linux/io-64-nonatomic-lo-hi.h>
29 /* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
52 		 * 11    MCH Thermal Sensor Event
55 		 *  9    LOCK to non-DRAM Memory Flag (LCKF)
59 		 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
60 		 *  0    Single-bit DRAM ECC Error Flag (DSERR)
67 /* Intel  MMIO register space - device 0 function 0 - MMR space */
113 	if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */  in how_many_channels()
170 	pdev = to_pci_dev(mci->pdev);  in i3200_clear_error_info()
184 	struct i3200_priv *priv = mci->pvt_info;  in i3200_get_and_clear_error_info()
185 	void __iomem *window = priv->window;  in i3200_get_and_clear_error_info()
187 	pdev = to_pci_dev(mci->pdev);  in i3200_get_and_clear_error_info()
194 	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);  in i3200_get_and_clear_error_info()
195 	if (!(info->errsts & I3200_ERRSTS_BITS))  in i3200_get_and_clear_error_info()
198 	info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);  in i3200_get_and_clear_error_info()
200 		info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);  in i3200_get_and_clear_error_info()
202 	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);  in i3200_get_and_clear_error_info()
210 	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {  in i3200_get_and_clear_error_info()
211 		info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);  in i3200_get_and_clear_error_info()
213 			info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);  in i3200_get_and_clear_error_info()
225 	if (!(info->errsts & I3200_ERRSTS_BITS))  in i3200_process_error_info()
228 	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {  in i3200_process_error_info()
230 				     -1, -1, -1, "UE overwrote CE", "");  in i3200_process_error_info()
231 		info->errsts = info->errsts2;  in i3200_process_error_info()
235 		log = info->eccerrlog[channel];  in i3200_process_error_info()
240 					     -1, -1,  in i3200_process_error_info()
246 					     -1, -1,  in i3200_process_error_info()
312 	return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;  in i3200_is_stacked()
326 		n -= drbs[channel][rank - 1];  in drb_to_nr_pages()
328 	drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])  in drb_to_nr_pages()
329 		n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];  in drb_to_nr_pages()
331 	n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);  in drb_to_nr_pages()
350 		return -ENODEV;  in i3200_probe1()
364 		return -ENOMEM;  in i3200_probe1()
368 	mci->pdev = &pdev->dev;  in i3200_probe1()
369 	mci->mtype_cap = MEM_FLAG_DDR2;  in i3200_probe1()
371 	mci->edac_ctl_cap = EDAC_FLAG_SECDED;  in i3200_probe1()
372 	mci->edac_cap = EDAC_FLAG_SECDED;  in i3200_probe1()
374 	mci->mod_name = EDAC_MOD_STR;  in i3200_probe1()
375 	mci->ctl_name = i3200_devs[dev_idx].ctl_name;  in i3200_probe1()
376 	mci->dev_name = pci_name(pdev);  in i3200_probe1()
377 	mci->edac_check = i3200_check;  in i3200_probe1()
378 	mci->ctl_page_to_phys = NULL;  in i3200_probe1()
379 	priv = mci->pvt_info;  in i3200_probe1()
380 	priv->window = window;  in i3200_probe1()
403 			dimm->nr_pages = nr_pages;  in i3200_probe1()
404 			dimm->grain = nr_pages << PAGE_SHIFT;  in i3200_probe1()
405 			dimm->mtype = MEM_DDR2;  in i3200_probe1()
406 			dimm->dtype = DEV_UNKNOWN;  in i3200_probe1()
407 			dimm->edac_mode = EDAC_UNKNOWN;  in i3200_probe1()
413 	rc = -ENODEV;  in i3200_probe1()
438 		return -EIO;  in i3200_init_one()
440 	rc = i3200_probe1(pdev, ent->driver_data);  in i3200_init_one()
454 	mci = edac_mc_del_mc(&pdev->dev);  in i3200_remove_one()
458 	priv = mci->pvt_info;  in i3200_remove_one()
459 	iounmap(priv->window);  in i3200_remove_one()
503 			pci_rc = -ENODEV;  in i3200_init()
510 			pci_rc = -ENODEV;  in i3200_init()
542 MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");