23 #define I10NM_GET_SCK_BAR(d, reg)	\  argument
24 	pci_read_config_dword((d)->uracu, 0xd0, &(reg))
25 #define I10NM_GET_IMC_BAR(d, i, reg)		\  argument
26 	pci_read_config_dword((d)->uracu,	\
28 #define I10NM_GET_SAD(d, offset, i, reg)\  argument
29 	pci_read_config_dword((d)->sad_all, (offset) + (i) * \
31 #define I10NM_GET_HBM_IMC_BAR(d, reg)	\  argument
32 	pci_read_config_dword((d)->uracu, 0xd4, &(reg))
33 #define I10NM_GET_CAPID3_CFG(d, reg)	\  argument
34 	pci_read_config_dword((d)->pcu_cr3,	\
36 #define I10NM_GET_CAPID5_CFG(d, reg)	\  argument
37 	pci_read_config_dword((d)->pcu_cr3,	\
84 	.set_num = 2,
94 	.over_mask	= BIT(2),
116 	.over_mask	= BIT(2),
127 	.set_num = 2,
137 	.over_mask	= BIT(2),
148 	.set_num = 2,
158 	.over_mask	= BIT(2),
181 	.over_mask	= BIT(2),
199 		i10nm_printk(KERN_ERR, "Invalid readd RRL 0x%x width %d\n", offset, width);  in read_imc_reg()
210 		i10nm_printk(KERN_ERR, "Invalid write RRL 0x%x width %d\n", offset, width);  in write_imc_reg()
310 	struct skx_dev *d;  in enable_retry_rd_err_log()  local
313 	edac_dbg(2, "\n");  in enable_retry_rd_err_log()
315 	list_for_each_entry(d, i10nm_edac_list, list) {  in enable_retry_rd_err_log()
318 			enable_rrls_ddr(&d->imc[i], enable);  in enable_retry_rd_err_log()
322 			enable_rrls_hbm(&d->imc[i], enable);  in enable_retry_rd_err_log()
364 			if (retry_rd_err_log == 2 && !j && (log & status_mask))  in show_retry_rd_err_log()
406 		edac_dbg(2, "No device %02x:%02x.%x\n",  in pci_get_dev_wrapper()
412 		edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",  in pci_get_dev_wrapper()
436 	struct skx_dev *d;  in i10nm_get_imc_num()  local
439 	list_for_each_entry(d, i10nm_edac_list, list) {  in i10nm_get_imc_num()
440 		d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->pcu_cr3_bdf.bus],  in i10nm_get_imc_num()
443 		if (!d->pcu_cr3)  in i10nm_get_imc_num()
446 		if (I10NM_GET_CAPID5_CFG(d, reg))  in i10nm_get_imc_num()
453 			edac_dbg(2, "Get DDR CH number: %d\n", chan_num);  in i10nm_get_imc_num()
455 			i10nm_printk(KERN_NOTICE, "Get DDR CH numbers: %d, %d\n", chan_num, n);  in i10nm_get_imc_num()
477 			edac_dbg(2, "Set DDR MC number: %d", imc_num);  in i10nm_get_imc_num()
497 	struct skx_dev *d;  in i10nm_check_2lm()  local
501 	list_for_each_entry(d, i10nm_edac_list, list) {  in i10nm_check_2lm()
502 		d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->sad_all_bdf.bus],  in i10nm_check_2lm()
505 		if (!d->sad_all)  in i10nm_check_2lm()
509 			I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg);  in i10nm_check_2lm()
511 				edac_dbg(2, "2-level memory configuration.\n");  in i10nm_check_2lm()
522  * Refer to SDM vol3B 17.11.3/17.13.2 Intel IMC MC error codes for IA32_MCi_STATUS.
600 	struct skx_dev *d;  in i10nm_mc_decode()  local
606 	list_for_each_entry(d, i10nm_edac_list, list) {  in i10nm_mc_decode()
607 		if (d->imc[0].src_id == m->socketid) {  in i10nm_mc_decode()
609 			res->dev = d;  in i10nm_mc_decode()
618 		res->channel      = bank % 2;  in i10nm_mc_decode()
619 		res->column       = GET_BITFIELD(m->misc, 9, 18) << 2;  in i10nm_mc_decode()
623 		res->bank_group  |= GET_BITFIELD(m->misc, 44, 44) << 2;  in i10nm_mc_decode()
625 		res->dimm         = res->rank >> 2;  in i10nm_mc_decode()
630 		res->imc          = bank / 2;  in i10nm_mc_decode()
631 		res->channel      = bank % 2;  in i10nm_mc_decode()
632 		res->column       = GET_BITFIELD(m->misc, 9, 18) << 2;  in i10nm_mc_decode()
636 		res->bank_group  |= GET_BITFIELD(m->misc, 41, 41) << 2;  in i10nm_mc_decode()
645 		skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",  in i10nm_mc_decode()
656  * @d            : The pointer to the structure of CPU socket EDAC device.
662 static struct pci_dev *get_gnr_mdev(struct skx_dev *d, int logical_idx, int *physical_idx)  in get_gnr_mdev()  argument
673 		mdev = pci_get_dev_wrapper(d->seg,  in get_gnr_mdev()
674 					   d->bus[res_cfg->ddr_mdev_bdf.bus],  in get_gnr_mdev()
703  * @d      : The pointer to the structure of CPU socket EDAC device.
710 static struct pci_dev *get_ddr_munit(struct skx_dev *d, int i, u32 *offset, unsigned long *size)  in get_ddr_munit()  argument
718 		if (I10NM_GET_IMC_BAR(d, 0, reg)) {  in get_ddr_munit()
723 		mdev = get_gnr_mdev(d, i, &physical_idx);  in get_ddr_munit()
734 		if (I10NM_GET_IMC_BAR(d, i, reg)) {  in get_ddr_munit()
735 			i10nm_printk(KERN_ERR, "Failed to get mc%d bar\n", i);  in get_ddr_munit()
739 		mdev = pci_get_dev_wrapper(d->seg,  in get_ddr_munit()
740 					   d->bus[res_cfg->ddr_mdev_bdf.bus],  in get_ddr_munit()
769 			edac_dbg(1, "ch%d mcmtr reg %x\n", i, mcmtr);  in i10nm_imc_absent()
794 	struct skx_dev *d;  in i10nm_get_ddr_munits()  local
799 	list_for_each_entry(d, i10nm_edac_list, list) {  in i10nm_get_ddr_munits()
800 		d->util_all = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->util_all_bdf.bus],  in i10nm_get_ddr_munits()
803 		if (!d->util_all)  in i10nm_get_ddr_munits()
806 		d->uracu = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->uracu_bdf.bus],  in i10nm_get_ddr_munits()
809 		if (!d->uracu)  in i10nm_get_ddr_munits()
812 		if (I10NM_GET_SCK_BAR(d, reg)) {  in i10nm_get_ddr_munits()
818 		edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",  in i10nm_get_ddr_munits()
822 			mdev = get_ddr_munit(d, i, &off, &size);  in i10nm_get_ddr_munits()
831 			edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",  in i10nm_get_ddr_munits()
841 			d->imc[lmc].mbase = mbase;  in i10nm_get_ddr_munits()
842 			if (i10nm_imc_absent(&d->imc[lmc])) {  in i10nm_get_ddr_munits()
845 				d->imc[lmc].mbase = NULL;  in i10nm_get_ddr_munits()
846 				edac_dbg(2, "Skip absent mc%d\n", i);  in i10nm_get_ddr_munits()
849 				d->imc[lmc].mdev = mdev;  in i10nm_get_ddr_munits()
851 					skx_set_mc_mapping(d, i, lmc);  in i10nm_get_ddr_munits()
860 static bool i10nm_check_hbm_imc(struct skx_dev *d)  in i10nm_check_hbm_imc()  argument
864 	if (I10NM_GET_CAPID3_CFG(d, reg)) {  in i10nm_check_hbm_imc()
877 	struct skx_dev *d;  in i10nm_get_hbm_munits()  local
881 	list_for_each_entry(d, i10nm_edac_list, list) {  in i10nm_get_hbm_munits()
882 		if (!d->pcu_cr3)  in i10nm_get_hbm_munits()
885 		if (!i10nm_check_hbm_imc(d)) {  in i10nm_get_hbm_munits()
890 		if (I10NM_GET_SCK_BAR(d, reg)) {  in i10nm_get_hbm_munits()
896 		if (I10NM_GET_HBM_IMC_BAR(d, reg)) {  in i10nm_get_hbm_munits()
905 			mdev = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->hbm_mdev_bdf.bus],  in i10nm_get_hbm_munits()
916 			d->imc[lmc].mdev = mdev;  in i10nm_get_hbm_munits()
919 			edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n",  in i10nm_get_hbm_munits()
924 				pci_dev_put(d->imc[lmc].mdev);  in i10nm_get_hbm_munits()
925 				d->imc[lmc].mdev = NULL;  in i10nm_get_hbm_munits()
932 			d->imc[lmc].mbase = mbase;  in i10nm_get_hbm_munits()
933 			d->imc[lmc].hbm_mc = true;  in i10nm_get_hbm_munits()
935 			mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0);  in i10nm_get_hbm_munits()
937 				iounmap(d->imc[lmc].mbase);  in i10nm_get_hbm_munits()
938 				d->imc[lmc].mbase = NULL;  in i10nm_get_hbm_munits()
939 				d->imc[lmc].hbm_mc = false;  in i10nm_get_hbm_munits()
940 				pci_dev_put(d->imc[lmc].mdev);  in i10nm_get_hbm_munits()
941 				d->imc[lmc].mdev = NULL;  in i10nm_get_hbm_munits()
959 	.ddr_chan_num		= 2,
960 	.ddr_dimm_num		= 2,
977 	.ddr_chan_num		= 2,
978 	.ddr_dimm_num		= 2,
995 	.ddr_chan_num		= 2,
996 	.ddr_dimm_num		= 2,
998 	.hbm_chan_num		= 2,
1021 	.ddr_dimm_num		= 2,
1056 	edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);  in i10nm_check_ecc()
1058 	return !!GET_BITFIELD(mcmtr, 2, 2);  in i10nm_check_ecc()
1065 	edac_dbg(1, "mc%d ch%d mcmtr reg %x\n", imc->mc, chan, mcmtr);  in i10nm_channel_disabled()
1084 			edac_dbg(1, "mc%d ch%d is disabled.\n", imc->mc, i);  in i10nm_get_dimm_config()
1096 			edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",  in i10nm_get_dimm_config()
1107 			i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",  in i10nm_get_dimm_config()
1127 	struct skx_dev *d;  in i10nm_init()  local
1132 	edac_dbg(2, "\n");  in i10nm_init()
1178 	list_for_each_entry(d, i10nm_edac_list, list) {  in i10nm_init()
1179 		rc = skx_get_src_id(d, 0xf8, &src_id);  in i10nm_init()
1183 		edac_dbg(2, "src_id = %d\n", src_id);  in i10nm_init()
1185 			if (!d->imc[i].mdev)  in i10nm_init()
1188 			d->imc[i].mc  = mc++;  in i10nm_init()
1189 			d->imc[i].lmc = i;  in i10nm_init()
1190 			d->imc[i].src_id = src_id;  in i10nm_init()
1191 			if (d->imc[i].hbm_mc) {  in i10nm_init()
1192 				d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;  in i10nm_init()
1193 				d->imc[i].num_channels = cfg->hbm_chan_num;  in i10nm_init()
1194 				d->imc[i].num_dimms    = cfg->hbm_dimm_num;  in i10nm_init()
1196 				d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;  in i10nm_init()
1197 				d->imc[i].num_channels = cfg->ddr_chan_num;  in i10nm_init()
1198 				d->imc[i].num_dimms    = cfg->ddr_dimm_num;  in i10nm_init()
1201 			rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,  in i10nm_init()
1219 		if (retry_rd_err_log == 2)  in i10nm_init()
1235 	edac_dbg(2, "\n");  in i10nm_exit()
1239 		if (retry_rd_err_log == 2)  in i10nm_exit()
1263 		i10nm_printk(KERN_NOTICE, "Decoding errors via MCA banks for 2LM isn't supported yet\n");  in set_decoding_via_mca()
1281 …t), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to…