Lines Matching full:row
79 #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
80 #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
82 * 31 Device width row 7 0=x8 1=x4
83 * 27 Device width row 6
84 * 23 Device width row 5
85 * 19 Device width row 4
86 * 15 Device width row 3
87 * 11 Device width row 2
88 * 7 Device width row 1
89 * 3 Device width row 0
207 int row; in process_ce() local
218 row = edac_mc_find_csrow_by_page(mci, page); in process_ce()
222 row, channel, -1, "e7xxx CE", ""); in process_ce()
235 int row; in process_ue() local
242 row = edac_mc_find_csrow_by_page(mci, block_page); in process_ue()
245 row, -1, -1, "e7xxx UE", ""); in process_ue()
371 /* The dram row boundary (DRB) reg values are boundary address in e7xxx_init_csrows()
372 * for each DRAM row with a granularity of 32 or 64MB (single/dual in e7xxx_init_csrows()