26 #define REG_OFFSET_FEATURE_CONFIG			0x130
27 #define REG_OFFSET_ECC_ERRC_COUNT_31_00		0x158
28 #define REG_OFFSET_ECC_ERRC_COUNT_63_32		0x15C
29 #define REG_OFFSET_ECC_ERRD_COUNT_31_00		0x160
30 #define REG_OFFSET_ECC_ERRD_COUNT_63_32		0x164
31 #define REG_OFFSET_INTERRUPT_CONTROL			0x500
32 #define REG_OFFSET_INTERRUPT_CLR			0x508
33 #define REG_OFFSET_INTERRUPT_STATUS			0x510
34 #define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00	0x528
35 #define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32	0x52C
36 #define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00	0x530
37 #define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32	0x534
38 #define REG_OFFSET_ADDRESS_CONTROL_NOW			0x1010
39 #define REG_OFFSET_MEMORY_TYPE_NOW			0x1128
40 #define REG_OFFSET_SCRUB_CONTROL0_NOW			0x1170
41 #define REG_OFFSET_FORMAT_CONTROL			0x18
44 #define RAM_ECC_INT_CE_BIT			BIT(0)
54 #define MEMORY_WIDTH_MASK			GENMASK(1, 0)
55 #define SCRUB_TRIGGER0_NEXT_MASK		GENMASK(1, 0)
56 #define REG_FIELD_DRAM_ECC_ENABLED		GENMASK(1, 0)
57 #define REG_FIELD_MEMORY_TYPE			GENMASK(2, 0)
59 #define REG_FIELD_ADDRESS_CONTROL_COL		GENMASK(2,  0)
63 #define REG_FIELD_ERR_INFO_LOW_VALID		BIT(0)
67 #define REG_FIELD_ERR_INFO_HIGH_BANK		GENMASK(3, 0)
99 	DEV_WIDTH_X4 = 0,
190 	u32 total = 0;  in dmc520_calc_dram_ecc_error()
193 	while (value > 0) {  in dmc520_calc_dram_ecc_error()
194 		total += (value & 0xFF);  in dmc520_calc_dram_ecc_error()
215 	dmc520_write_reg(pvt, 0, reg_offset_low);  in dmc520_get_dram_ecc_error_count()
216 	dmc520_write_reg(pvt, 0, reg_offset_high);  in dmc520_get_dram_ecc_error_count()
240 	valid = (FIELD_GET(REG_FIELD_ERR_INFO_LOW_VALID, reg_val_low) != 0) &&  in dmc520_get_dram_ecc_error_info()
241 		(FIELD_GET(REG_FIELD_ERR_INFO_HIGH_VALID, reg_val_high) != 0);  in dmc520_get_dram_ecc_error_info()
249 		memset(info, 0, sizeof(*info));  in dmc520_get_dram_ecc_error_info()
279 	u32 mem_width_in_bytes = 0;  in dmc520_get_memory_width()
387 			     mci, cnt, 0, 0, 0, info.rank, -1, -1,  in dmc520_handle_dram_ecc_errors()
431 	u32 mask = 0;  in dmc520_isr()
434 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {  in dmc520_isr()
459 	for (row = 0; row < mci->nr_csrows; row++) {  in dmc520_init_csrow()
462 		for (ch = 0; ch < csi->nr_channels; ch++) {  in dmc520_init_csrow()
477 	int masks[NUMBER_OF_IRQS] = { 0 };  in dmc520_edac_probe()
482 	u32 irq_mask_all = 0;  in dmc520_edac_probe()
490 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {  in dmc520_edac_probe()
494 		if (irq >= 0) {  in dmc520_edac_probe()
496 			edac_dbg(0, "Discovered %s, irq: %d.\n", dmc520_irq_configs[idx].name, irq);  in dmc520_edac_probe()
507 	reg_base = devm_platform_ioremap_resource(pdev, 0);  in dmc520_edac_probe()
514 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;  in dmc520_edac_probe()
515 	layers[0].size = dmc520_get_rank_count(reg_base);  in dmc520_edac_probe()
516 	layers[0].is_virt_csrow = true;  in dmc520_edac_probe()
557 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {  in dmc520_edac_probe()
559 		if (irq >= 0) {  in dmc520_edac_probe()
563 			if (ret < 0) {  in dmc520_edac_probe()
590 	return 0;  in dmc520_edac_probe()
593 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {  in dmc520_edac_probe()
605 	u32 reg_val, idx, irq_mask_all = 0;  in dmc520_edac_remove()
618 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {  in dmc520_edac_remove()
619 		if (pvt->irqs[idx] >= 0) {  in dmc520_edac_remove()