Lines Matching full:pvt
18 static inline u32 get_umc_reg(struct amd64_pvt *pvt, u32 reg) in get_umc_reg() argument
20 if (!pvt->flags.zn_regs_v2) in get_umc_reg()
103 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
107 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
108 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
110 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
127 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
130 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
143 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg()
155 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
156 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
167 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
188 static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) in __set_scrub_rate() argument
216 if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
217 f15h_select_dct(pvt, 0); in __set_scrub_rate()
218 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
219 f15h_select_dct(pvt, 1); in __set_scrub_rate()
220 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
222 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
233 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate() local
236 if (pvt->fam == 0xf) in set_scrub_rate()
239 if (pvt->fam == 0x15) { in set_scrub_rate()
241 if (pvt->model < 0x10) in set_scrub_rate()
242 f15h_select_dct(pvt, 0); in set_scrub_rate()
244 if (pvt->model == 0x60) in set_scrub_rate()
247 return __set_scrub_rate(pvt, bw, min_scrubrate); in set_scrub_rate()
252 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate() local
256 if (pvt->fam == 0x15) { in get_scrub_rate()
258 if (pvt->model < 0x10) in get_scrub_rate()
259 f15h_select_dct(pvt, 0); in get_scrub_rate()
261 if (pvt->model == 0x60) in get_scrub_rate()
262 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
264 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
266 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
284 static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) in base_limit_match() argument
296 return ((addr >= get_dram_base(pvt, nid)) && in base_limit_match()
297 (addr <= get_dram_limit(pvt, nid))); in base_limit_match()
309 struct amd64_pvt *pvt; in find_mc_by_sys_addr() local
317 pvt = mci->pvt_info; in find_mc_by_sys_addr()
324 intlv_en = dram_intlv_en(pvt, 0); in find_mc_by_sys_addr()
328 if (base_limit_match(pvt, sys_addr, node_id)) in find_mc_by_sys_addr()
344 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) in find_mc_by_sys_addr()
352 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { in find_mc_by_sys_addr()
373 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
379 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
380 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
381 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
390 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
391 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
392 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
393 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
408 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
409 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
412 if (pvt->fam == 0x15) in get_cs_base_and_mask()
429 #define for_each_chip_select(i, dct, pvt) \ argument
430 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
432 #define chip_select_base(i, dct, pvt) \ argument
433 pvt->csels[dct].csbases[i]
435 #define for_each_chip_select_mask(i, dct, pvt) \ argument
436 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
439 for (i = 0; i < pvt->max_mcs; i++)
447 struct amd64_pvt *pvt; in input_addr_to_csrow() local
451 pvt = mci->pvt_info; in input_addr_to_csrow()
453 for_each_chip_select(csrow, 0, pvt) { in input_addr_to_csrow()
454 if (!csrow_enabled(csrow, 0, pvt)) in input_addr_to_csrow()
457 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); in input_addr_to_csrow()
464 pvt->mc_node_id); in input_addr_to_csrow()
470 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
494 struct amd64_pvt *pvt = mci->pvt_info; in get_dram_hole_info() local
497 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in get_dram_hole_info()
499 pvt->ext_model, pvt->mc_node_id); in get_dram_hole_info()
504 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in get_dram_hole_info()
509 if (!dhar_valid(pvt)) { in get_dram_hole_info()
511 pvt->mc_node_id); in get_dram_hole_info()
533 *hole_base = dhar_base(pvt); in get_dram_hole_info()
536 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in get_dram_hole_info()
537 : k8_dhar_offset(pvt); in get_dram_hole_info()
540 pvt->mc_node_id, (unsigned long)*hole_base, in get_dram_hole_info()
552 struct amd64_pvt *pvt = mci->pvt_info; \
554 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
603 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_show() local
604 return sprintf(buf, "0x%x\n", pvt->injection.section); in inject_section_show()
618 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_store() local
631 pvt->injection.section = (u32) value; in inject_section_store()
639 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_show() local
640 return sprintf(buf, "0x%x\n", pvt->injection.word); in inject_word_show()
654 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_store() local
667 pvt->injection.word = (u32) value; in inject_word_store()
676 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_show() local
677 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); in inject_ecc_vector_show()
690 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_store() local
703 pvt->injection.bit_map = (u32) value; in inject_ecc_vector_store()
708 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
716 struct amd64_pvt *pvt = mci->pvt_info; in inject_read_store() local
726 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_read_store()
728 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_read_store()
730 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection); in inject_read_store()
733 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_read_store()
741 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
749 struct amd64_pvt *pvt = mci->pvt_info; in inject_write_store() local
759 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_write_store()
761 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_write_store()
763 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection); in inject_write_store()
772 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_write_store()
776 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp); in inject_write_store()
812 struct amd64_pvt *pvt = mci->pvt_info; in inj_is_visible() local
815 if (pvt->fam >= 0x10 && pvt->fam <= 0x16) in inj_is_visible()
858 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr() local
862 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
913 struct amd64_pvt *pvt; in dram_addr_to_input_addr() local
917 pvt = mci->pvt_info; in dram_addr_to_input_addr()
923 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); in dram_addr_to_input_addr()
1000 static int gpu_get_node_map(struct amd64_pvt *pvt) in gpu_get_node_map() argument
1011 if (pvt->F3->device != PCI_DEVICE_ID_AMD_MI200_DF_F3) in gpu_get_node_map()
1063 static unsigned long dct_determine_edac_cap(struct amd64_pvt *pvt) in dct_determine_edac_cap() argument
1068 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in dct_determine_edac_cap()
1072 if (pvt->dclr0 & BIT(bit)) in dct_determine_edac_cap()
1078 static unsigned long umc_determine_edac_cap(struct amd64_pvt *pvt) in umc_determine_edac_cap() argument
1084 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in umc_determine_edac_cap()
1090 if (pvt->umc[i].umc_cfg & BIT(12)) in umc_determine_edac_cap()
1104 static void dct_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in dct_debug_display_dimm_sizes() argument
1106 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
1107 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in dct_debug_display_dimm_sizes()
1110 if (pvt->fam == 0xf) { in dct_debug_display_dimm_sizes()
1112 if (pvt->ext_model < K8_REV_F) in dct_debug_display_dimm_sizes()
1118 if (pvt->fam == 0x10) { in dct_debug_display_dimm_sizes()
1119 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in dct_debug_display_dimm_sizes()
1120 : pvt->dbam0; in dct_debug_display_dimm_sizes()
1121 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? in dct_debug_display_dimm_sizes()
1122 pvt->csels[1].csbases : in dct_debug_display_dimm_sizes()
1123 pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
1125 dbam = pvt->dbam0; in dct_debug_display_dimm_sizes()
1126 dcsb = pvt->csels[1].csbases; in dct_debug_display_dimm_sizes()
1143 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in dct_debug_display_dimm_sizes()
1149 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in dct_debug_display_dimm_sizes()
1160 static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) in debug_dump_dramcfg_low() argument
1164 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
1165 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
1181 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
1201 static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) in umc_get_cs_mode() argument
1206 if (csrow_enabled(2 * dimm, ctrl, pvt)) in umc_get_cs_mode()
1209 if (csrow_enabled(2 * dimm + 1, ctrl, pvt)) in umc_get_cs_mode()
1213 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt)) in umc_get_cs_mode()
1221 for_each_chip_select(base, ctrl, pvt) in umc_get_cs_mode()
1222 count += csrow_enabled(base, ctrl, pvt); in umc_get_cs_mode()
1225 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) { in umc_get_cs_mode()
1269 static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in umc_addr_mask_to_cs_size() argument
1308 if (!pvt->flags.zn_regs_v2) in umc_addr_mask_to_cs_size()
1313 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1315 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1320 static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in umc_debug_display_dimm_sizes() argument
1330 cs_mode = umc_get_cs_mode(dimm, ctrl, pvt); in umc_debug_display_dimm_sizes()
1332 size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0); in umc_debug_display_dimm_sizes()
1333 size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1); in umc_debug_display_dimm_sizes()
1341 static void umc_dump_misc_regs(struct amd64_pvt *pvt) in umc_dump_misc_regs() argument
1347 umc = &pvt->umc[i]; in umc_dump_misc_regs()
1365 umc_debug_display_dimm_sizes(pvt, i); in umc_dump_misc_regs()
1369 static void dct_dump_misc_regs(struct amd64_pvt *pvt) in dct_dump_misc_regs() argument
1371 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in dct_dump_misc_regs()
1374 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in dct_dump_misc_regs()
1377 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in dct_dump_misc_regs()
1378 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in dct_dump_misc_regs()
1380 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in dct_dump_misc_regs()
1382 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in dct_dump_misc_regs()
1385 pvt->dhar, dhar_base(pvt), in dct_dump_misc_regs()
1386 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in dct_dump_misc_regs()
1387 : f10_dhar_offset(pvt)); in dct_dump_misc_regs()
1389 dct_debug_display_dimm_sizes(pvt, 0); in dct_dump_misc_regs()
1392 if (pvt->fam == 0xf) in dct_dump_misc_regs()
1395 dct_debug_display_dimm_sizes(pvt, 1); in dct_dump_misc_regs()
1398 if (!dct_ganging_enabled(pvt)) in dct_dump_misc_regs()
1399 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in dct_dump_misc_regs()
1401 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); in dct_dump_misc_regs()
1403 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dct_dump_misc_regs()
1409 static void dct_prep_chip_selects(struct amd64_pvt *pvt) in dct_prep_chip_selects() argument
1411 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in dct_prep_chip_selects()
1412 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in dct_prep_chip_selects()
1413 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in dct_prep_chip_selects()
1414 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in dct_prep_chip_selects()
1415 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in dct_prep_chip_selects()
1416 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in dct_prep_chip_selects()
1418 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in dct_prep_chip_selects()
1419 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in dct_prep_chip_selects()
1423 static void umc_prep_chip_selects(struct amd64_pvt *pvt) in umc_prep_chip_selects() argument
1428 pvt->csels[umc].b_cnt = 4; in umc_prep_chip_selects()
1429 pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2; in umc_prep_chip_selects()
1433 static void umc_read_base_mask(struct amd64_pvt *pvt) in umc_read_base_mask() argument
1448 for_each_chip_select(cs, umc, pvt) { in umc_read_base_mask()
1449 base = &pvt->csels[umc].csbases[cs]; in umc_read_base_mask()
1450 base_sec = &pvt->csels[umc].csbases_sec[cs]; in umc_read_base_mask()
1455 if (!amd_smn_read(pvt->mc_node_id, base_reg, &tmp)) { in umc_read_base_mask()
1461 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, &tmp)) { in umc_read_base_mask()
1469 umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(pvt, UMCCH_ADDR_MASK_SEC); in umc_read_base_mask()
1471 for_each_chip_select_mask(cs, umc, pvt) { in umc_read_base_mask()
1472 mask = &pvt->csels[umc].csmasks[cs]; in umc_read_base_mask()
1473 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in umc_read_base_mask()
1478 if (!amd_smn_read(pvt->mc_node_id, mask_reg, &tmp)) { in umc_read_base_mask()
1484 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, &tmp)) { in umc_read_base_mask()
1496 static void dct_read_base_mask(struct amd64_pvt *pvt) in dct_read_base_mask() argument
1500 for_each_chip_select(cs, 0, pvt) { in dct_read_base_mask()
1503 u32 *base0 = &pvt->csels[0].csbases[cs]; in dct_read_base_mask()
1504 u32 *base1 = &pvt->csels[1].csbases[cs]; in dct_read_base_mask()
1506 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) in dct_read_base_mask()
1510 if (pvt->fam == 0xf) in dct_read_base_mask()
1513 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) in dct_read_base_mask()
1515 cs, *base1, (pvt->fam == 0x10) ? reg1 in dct_read_base_mask()
1519 for_each_chip_select_mask(cs, 0, pvt) { in dct_read_base_mask()
1522 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in dct_read_base_mask()
1523 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in dct_read_base_mask()
1525 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) in dct_read_base_mask()
1529 if (pvt->fam == 0xf) in dct_read_base_mask()
1532 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) in dct_read_base_mask()
1534 cs, *mask1, (pvt->fam == 0x10) ? reg1 in dct_read_base_mask()
1539 static void umc_determine_memory_type(struct amd64_pvt *pvt) in umc_determine_memory_type() argument
1545 umc = &pvt->umc[i]; in umc_determine_memory_type()
1556 if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) { in umc_determine_memory_type()
1576 static void dct_determine_memory_type(struct amd64_pvt *pvt) in dct_determine_memory_type() argument
1580 switch (pvt->fam) { in dct_determine_memory_type()
1582 if (pvt->ext_model >= K8_REV_F) in dct_determine_memory_type()
1585 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in dct_determine_memory_type()
1589 if (pvt->dchr0 & DDR3_MODE) in dct_determine_memory_type()
1592 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in dct_determine_memory_type()
1596 if (pvt->model < 0x60) in dct_determine_memory_type()
1608 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); in dct_determine_memory_type()
1609 dcsm = pvt->csels[0].csmasks[0]; in dct_determine_memory_type()
1612 pvt->dram_type = MEM_DDR4; in dct_determine_memory_type()
1613 else if (pvt->dclr0 & BIT(16)) in dct_determine_memory_type()
1614 pvt->dram_type = MEM_DDR3; in dct_determine_memory_type()
1616 pvt->dram_type = MEM_LRDDR3; in dct_determine_memory_type()
1618 pvt->dram_type = MEM_RDDR3; in dct_determine_memory_type()
1626 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in dct_determine_memory_type()
1627 pvt->dram_type = MEM_EMPTY; in dct_determine_memory_type()
1630 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in dct_determine_memory_type()
1634 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in dct_determine_memory_type()
1638 static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) in get_error_address() argument
1650 pvt = mci->pvt_info; in get_error_address()
1652 if (pvt->fam == 0xf) { in get_error_address()
1662 if (pvt->fam == 0x15) { in get_error_address()
1671 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1686 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1719 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) in read_dram_base_limit_regs() argument
1727 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1728 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1730 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1733 if (!dram_rw(pvt, range)) in read_dram_base_limit_regs()
1736 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1737 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1740 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1743 nb = node_to_amd_nb(dram_dst_node(pvt, range)); in read_dram_base_limit_regs()
1747 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1749 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1760 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1763 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1765 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1768 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1776 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow() local
1800 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1841 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in k8_dbam_to_chip_select() argument
1844 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1846 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1850 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1945 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f10_dbam_to_chip_select() argument
1948 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1952 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1961 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_dbam_to_chip_select() argument
1970 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_m60h_dbam_to_chip_select() argument
1974 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1978 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1983 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
2003 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f16_dbam_to_chip_select() argument
2015 static void read_dram_ctl_register(struct amd64_pvt *pvt) in read_dram_ctl_register() argument
2018 if (pvt->fam == 0xf) in read_dram_ctl_register()
2021 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
2023 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
2026 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); in read_dram_ctl_register()
2028 if (!dct_ganging_enabled(pvt)) in read_dram_ctl_register()
2030 (dct_high_range_enabled(pvt) ? "yes" : "no")); in read_dram_ctl_register()
2033 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
2034 (dct_memory_cleared(pvt) ? "yes" : "no")); in read_dram_ctl_register()
2038 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
2039 dct_sel_interleave_addr(pvt)); in read_dram_ctl_register()
2042 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
2049 static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f15_m30h_determine_channel() argument
2063 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_determine_channel()
2080 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f1x_determine_channel() argument
2083 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
2085 if (dct_ganging_enabled(pvt)) in f1x_determine_channel()
2094 if (dct_interleave_enabled(pvt)) { in f1x_determine_channel()
2095 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f1x_determine_channel()
2117 if (dct_high_range_enabled(pvt)) in f1x_determine_channel()
2124 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, in f1x_get_norm_dct_addr() argument
2129 u64 dram_base = get_dram_base(pvt, range); in f1x_get_norm_dct_addr()
2130 u64 hole_off = f10_dhar_offset(pvt); in f1x_get_norm_dct_addr()
2131 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
2146 dct_sel_base_addr < dhar_base(pvt)) && in f1x_get_norm_dct_addr()
2147 dhar_valid(pvt) && in f1x_get_norm_dct_addr()
2162 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) in f1x_get_norm_dct_addr()
2175 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) in f10_process_possible_spare() argument
2179 if (online_spare_swap_done(pvt, dct) && in f10_process_possible_spare()
2180 csrow == online_spare_bad_dramcs(pvt, dct)) { in f10_process_possible_spare()
2182 for_each_chip_select(tmp_cs, dct, pvt) { in f10_process_possible_spare()
2183 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { in f10_process_possible_spare()
2203 struct amd64_pvt *pvt; in f1x_lookup_addr_in_dct() local
2212 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
2216 for_each_chip_select(csrow, dct, pvt) { in f1x_lookup_addr_in_dct()
2217 if (!csrow_enabled(csrow, dct, pvt)) in f1x_lookup_addr_in_dct()
2220 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
2231 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
2235 cs_found = f10_process_possible_spare(pvt, dct, csrow); in f1x_lookup_addr_in_dct()
2249 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) in f1x_swap_interleaved_region() argument
2253 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
2255 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
2259 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
2279 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f1x_match_to_this_node() argument
2288 u8 node_id = dram_dst_node(pvt, range); in f1x_match_to_this_node()
2289 u8 intlv_en = dram_intlv_en(pvt, range); in f1x_match_to_this_node()
2290 u32 intlv_sel = dram_intlv_sel(pvt, range); in f1x_match_to_this_node()
2293 range, sys_addr, get_dram_limit(pvt, range)); in f1x_match_to_this_node()
2295 if (dhar_valid(pvt) && in f1x_match_to_this_node()
2296 dhar_base(pvt) <= sys_addr && in f1x_match_to_this_node()
2306 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); in f1x_match_to_this_node()
2308 dct_sel_base = dct_sel_baseaddr(pvt); in f1x_match_to_this_node()
2314 if (dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
2315 !dct_ganging_enabled(pvt) && in f1x_match_to_this_node()
2319 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); in f1x_match_to_this_node()
2321 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, in f1x_match_to_this_node()
2330 if (dct_interleave_enabled(pvt) && in f1x_match_to_this_node()
2331 !dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
2332 !dct_ganging_enabled(pvt)) { in f1x_match_to_this_node()
2334 if (dct_sel_interleave_addr(pvt) != 1) { in f1x_match_to_this_node()
2335 if (dct_sel_interleave_addr(pvt) == 0x3) in f1x_match_to_this_node()
2359 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f15_m30h_match_to_this_node() argument
2369 u64 dhar_offset = f10_dhar_offset(pvt); in f15_m30h_match_to_this_node()
2370 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_match_to_this_node()
2371 u8 node_id = dram_dst_node(pvt, range); in f15_m30h_match_to_this_node()
2372 u8 intlv_en = dram_intlv_en(pvt, range); in f15_m30h_match_to_this_node()
2374 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2375 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2381 range, sys_addr, get_dram_limit(pvt, range)); in f15_m30h_match_to_this_node()
2383 if (!(get_dram_base(pvt, range) <= sys_addr) && in f15_m30h_match_to_this_node()
2384 !(get_dram_limit(pvt, range) >= sys_addr)) in f15_m30h_match_to_this_node()
2387 if (dhar_valid(pvt) && in f15_m30h_match_to_this_node()
2388 dhar_base(pvt) <= sys_addr && in f15_m30h_match_to_this_node()
2396 dct_base = (u64) dct_sel_baseaddr(pvt); in f15_m30h_match_to_this_node()
2410 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2411 channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en); in f15_m30h_match_to_this_node()
2413 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, in f15_m30h_match_to_this_node()
2453 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2459 f15h_select_dct(pvt, channel); in f15_m30h_match_to_this_node()
2468 * pvt->csels[1]. So we need to use '1' here to get correct info. in f15_m30h_match_to_this_node()
2481 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, in f1x_translate_sysaddr_to_cs() argument
2489 if (!dram_rw(pvt, range)) in f1x_translate_sysaddr_to_cs()
2492 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2493 cs_found = f15_m30h_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2497 else if ((get_dram_base(pvt, range) <= sys_addr) && in f1x_translate_sysaddr_to_cs()
2498 (get_dram_limit(pvt, range) >= sys_addr)) { in f1x_translate_sysaddr_to_cs()
2499 cs_found = f1x_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2518 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow() local
2522 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2533 if (dct_ganging_enabled(pvt)) in f1x_map_sysaddr_to_csrow()
2674 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome() local
2677 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2680 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2681 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2684 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2686 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2690 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2743 struct amd64_pvt *pvt; in decode_bus_error() local
2754 pvt = mci->pvt_info; in decode_bus_error()
2766 sys_addr = get_error_address(pvt, m); in decode_bus_error()
2771 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2799 struct amd64_pvt *pvt; in decode_umc_error() local
2809 pvt = mci->pvt_info; in decode_umc_error()
2830 pvt->ops->get_err_info(m, &err); in decode_umc_error()
2849 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
2853 reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2) in reserve_mc_sibling_devs() argument
2856 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2857 if (!pvt->F1) { in reserve_mc_sibling_devs()
2863 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2864 if (!pvt->F2) { in reserve_mc_sibling_devs()
2865 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2866 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2873 pci_ctl_dev = &pvt->F2->dev; in reserve_mc_sibling_devs()
2875 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2876 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2877 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2882 static void determine_ecc_sym_sz(struct amd64_pvt *pvt) in determine_ecc_sym_sz() argument
2884 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
2886 if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
2889 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
2891 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
2892 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
2895 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
2896 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2903 static void umc_read_mc_regs(struct amd64_pvt *pvt) in umc_read_mc_regs() argument
2905 u8 nid = pvt->mc_node_id; in umc_read_mc_regs()
2913 umc = &pvt->umc[i]; in umc_read_mc_regs()
2915 if (!amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &tmp)) in umc_read_mc_regs()
2936 static void dct_read_mc_regs(struct amd64_pvt *pvt) in dct_read_mc_regs() argument
2945 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in dct_read_mc_regs()
2946 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in dct_read_mc_regs()
2951 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in dct_read_mc_regs()
2952 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in dct_read_mc_regs()
2957 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in dct_read_mc_regs()
2959 read_dram_ctl_register(pvt); in dct_read_mc_regs()
2965 read_dram_base_limit_regs(pvt, range); in dct_read_mc_regs()
2967 rw = dram_rw(pvt, range); in dct_read_mc_regs()
2973 get_dram_base(pvt, range), in dct_read_mc_regs()
2974 get_dram_limit(pvt, range)); in dct_read_mc_regs()
2977 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", in dct_read_mc_regs()
2980 dram_intlv_sel(pvt, range), in dct_read_mc_regs()
2981 dram_dst_node(pvt, range)); in dct_read_mc_regs()
2984 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in dct_read_mc_regs()
2985 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in dct_read_mc_regs()
2987 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in dct_read_mc_regs()
2989 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in dct_read_mc_regs()
2990 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in dct_read_mc_regs()
2992 if (!dct_ganging_enabled(pvt)) { in dct_read_mc_regs()
2993 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in dct_read_mc_regs()
2994 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in dct_read_mc_regs()
2997 determine_ecc_sym_sz(pvt); in dct_read_mc_regs()
3034 static u32 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in dct_get_csrow_nr_pages() argument
3036 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in dct_get_csrow_nr_pages()
3042 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in dct_get_csrow_nr_pages()
3052 static u32 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) in umc_get_csrow_nr_pages() argument
3057 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt); in umc_get_csrow_nr_pages()
3059 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in umc_get_csrow_nr_pages()
3071 struct amd64_pvt *pvt = mci->pvt_info; in umc_init_csrows() local
3091 for_each_chip_select(cs, umc, pvt) { in umc_init_csrows()
3092 if (!csrow_enabled(cs, umc, pvt)) in umc_init_csrows()
3098 pvt->mc_node_id, cs); in umc_init_csrows()
3100 dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs); in umc_init_csrows()
3101 dimm->mtype = pvt->umc[umc].dram_type; in umc_init_csrows()
3115 struct amd64_pvt *pvt = mci->pvt_info; in dct_init_csrows() local
3123 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in dct_init_csrows()
3125 pvt->nbcfg = val; in dct_init_csrows()
3128 pvt->mc_node_id, val, in dct_init_csrows()
3134 for_each_chip_select(i, 0, pvt) { in dct_init_csrows()
3135 bool row_dct0 = !!csrow_enabled(i, 0, pvt); in dct_init_csrows()
3138 if (pvt->fam != 0xf) in dct_init_csrows()
3139 row_dct1 = !!csrow_enabled(i, 1, pvt); in dct_init_csrows()
3147 pvt->mc_node_id, i); in dct_init_csrows()
3150 nr_pages = dct_get_csrow_nr_pages(pvt, 0, i); in dct_init_csrows()
3155 if (pvt->fam != 0xf && row_dct1) { in dct_init_csrows()
3156 int row_dct1_pages = dct_get_csrow_nr_pages(pvt, 1, i); in dct_init_csrows()
3165 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in dct_init_csrows()
3166 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in dct_init_csrows()
3171 for (j = 0; j < pvt->max_mcs; j++) { in dct_init_csrows()
3173 dimm->mtype = pvt->dram_type; in dct_init_csrows()
3340 static bool dct_ecc_enabled(struct amd64_pvt *pvt) in dct_ecc_enabled() argument
3342 u16 nid = pvt->mc_node_id; in dct_ecc_enabled()
3347 amd64_read_pci_cfg(pvt->F3, NBCFG, &value); in dct_ecc_enabled()
3364 static bool umc_ecc_enabled(struct amd64_pvt *pvt) in umc_ecc_enabled() argument
3372 umc = &pvt->umc[i]; in umc_ecc_enabled()
3381 edac_dbg(3, "Node %d: DRAM ECC %s.\n", pvt->mc_node_id, (ecc_en ? "enabled" : "disabled")); in umc_ecc_enabled()
3387 umc_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) in umc_determine_edac_ctl_cap() argument
3392 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in umc_determine_edac_ctl_cap()
3393 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in umc_determine_edac_ctl_cap()
3394 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in umc_determine_edac_ctl_cap()
3396 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in umc_determine_edac_ctl_cap()
3397 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in umc_determine_edac_ctl_cap()
3419 struct amd64_pvt *pvt = mci->pvt_info; in dct_setup_mci_misc_attrs() local
3424 if (pvt->nbcap & NBCAP_SECDED) in dct_setup_mci_misc_attrs()
3427 if (pvt->nbcap & NBCAP_CHIPKILL) in dct_setup_mci_misc_attrs()
3430 mci->edac_cap = dct_determine_edac_cap(pvt); in dct_setup_mci_misc_attrs()
3432 mci->ctl_name = pvt->ctl_name; in dct_setup_mci_misc_attrs()
3433 mci->dev_name = pci_name(pvt->F3); in dct_setup_mci_misc_attrs()
3445 struct amd64_pvt *pvt = mci->pvt_info; in umc_setup_mci_misc_attrs() local
3450 umc_determine_edac_ctl_cap(mci, pvt); in umc_setup_mci_misc_attrs()
3452 mci->edac_cap = umc_determine_edac_cap(pvt); in umc_setup_mci_misc_attrs()
3454 mci->ctl_name = pvt->ctl_name; in umc_setup_mci_misc_attrs()
3455 mci->dev_name = pci_name(pvt->F3); in umc_setup_mci_misc_attrs()
3461 static int dct_hw_info_get(struct amd64_pvt *pvt) in dct_hw_info_get() argument
3463 int ret = reserve_mc_sibling_devs(pvt, pvt->f1_id, pvt->f2_id); in dct_hw_info_get()
3468 dct_prep_chip_selects(pvt); in dct_hw_info_get()
3469 dct_read_base_mask(pvt); in dct_hw_info_get()
3470 dct_read_mc_regs(pvt); in dct_hw_info_get()
3471 dct_determine_memory_type(pvt); in dct_hw_info_get()
3476 static int umc_hw_info_get(struct amd64_pvt *pvt) in umc_hw_info_get() argument
3478 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in umc_hw_info_get()
3479 if (!pvt->umc) in umc_hw_info_get()
3482 umc_prep_chip_selects(pvt); in umc_hw_info_get()
3483 umc_read_base_mask(pvt); in umc_hw_info_get()
3484 umc_read_mc_regs(pvt); in umc_hw_info_get()
3485 umc_determine_memory_type(pvt); in umc_hw_info_get()
3516 static int gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in gpu_addr_mask_to_cs_size() argument
3519 u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr]; in gpu_addr_mask_to_cs_size()
3524 static void gpu_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in gpu_debug_display_dimm_sizes() argument
3532 for_each_chip_select(cs, ctrl, pvt) { in gpu_debug_display_dimm_sizes()
3533 size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs); in gpu_debug_display_dimm_sizes()
3538 static void gpu_dump_misc_regs(struct amd64_pvt *pvt) in gpu_dump_misc_regs() argument
3544 umc = &pvt->umc[i]; in gpu_dump_misc_regs()
3551 gpu_debug_display_dimm_sizes(pvt, i); in gpu_dump_misc_regs()
3555 static u32 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in gpu_get_csrow_nr_pages() argument
3560 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in gpu_get_csrow_nr_pages()
3571 struct amd64_pvt *pvt = mci->pvt_info; in gpu_init_csrows() local
3576 for_each_chip_select(cs, umc, pvt) { in gpu_init_csrows()
3577 if (!csrow_enabled(cs, umc, pvt)) in gpu_init_csrows()
3583 pvt->mc_node_id, cs); in gpu_init_csrows()
3585 dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs); in gpu_init_csrows()
3587 dimm->mtype = pvt->dram_type; in gpu_init_csrows()
3596 struct amd64_pvt *pvt = mci->pvt_info; in gpu_setup_mci_misc_attrs() local
3603 mci->ctl_name = pvt->ctl_name; in gpu_setup_mci_misc_attrs()
3604 mci->dev_name = pci_name(pvt->F3); in gpu_setup_mci_misc_attrs()
3611 static bool gpu_ecc_enabled(struct amd64_pvt *pvt) in gpu_ecc_enabled() argument
3616 static inline u32 gpu_get_umc_base(struct amd64_pvt *pvt, u8 umc, u8 channel) in gpu_get_umc_base() argument
3638 return pvt->gpu_umc_base + (umc << 20) + ((channel % 4) << 12); in gpu_get_umc_base()
3641 static void gpu_read_mc_regs(struct amd64_pvt *pvt) in gpu_read_mc_regs() argument
3643 u8 nid = pvt->mc_node_id; in gpu_read_mc_regs()
3649 umc_base = gpu_get_umc_base(pvt, i, 0); in gpu_read_mc_regs()
3650 umc = &pvt->umc[i]; in gpu_read_mc_regs()
3663 static void gpu_read_base_mask(struct amd64_pvt *pvt) in gpu_read_base_mask() argument
3670 for_each_chip_select(cs, umc, pvt) { in gpu_read_base_mask()
3671 base_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_BASE_ADDR; in gpu_read_base_mask()
3672 base = &pvt->csels[umc].csbases[cs]; in gpu_read_base_mask()
3674 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) { in gpu_read_base_mask()
3679 mask_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_ADDR_MASK; in gpu_read_base_mask()
3680 mask = &pvt->csels[umc].csmasks[cs]; in gpu_read_base_mask()
3682 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) { in gpu_read_base_mask()
3690 static void gpu_prep_chip_selects(struct amd64_pvt *pvt) in gpu_prep_chip_selects() argument
3695 pvt->csels[umc].b_cnt = 8; in gpu_prep_chip_selects()
3696 pvt->csels[umc].m_cnt = 8; in gpu_prep_chip_selects()
3700 static int gpu_hw_info_get(struct amd64_pvt *pvt) in gpu_hw_info_get() argument
3704 ret = gpu_get_node_map(pvt); in gpu_hw_info_get()
3708 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in gpu_hw_info_get()
3709 if (!pvt->umc) in gpu_hw_info_get()
3712 gpu_prep_chip_selects(pvt); in gpu_hw_info_get()
3713 gpu_read_base_mask(pvt); in gpu_hw_info_get()
3714 gpu_read_mc_regs(pvt); in gpu_hw_info_get()
3719 static void hw_info_put(struct amd64_pvt *pvt) in hw_info_put() argument
3721 pci_dev_put(pvt->F1); in hw_info_put()
3722 pci_dev_put(pvt->F2); in hw_info_put()
3723 kfree(pvt->umc); in hw_info_put()
3752 static int per_family_init(struct amd64_pvt *pvt) in per_family_init() argument
3754 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3755 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3756 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3757 pvt->fam = boot_cpu_data.x86; in per_family_init()
3758 pvt->max_mcs = 2; in per_family_init()
3764 if (pvt->fam >= 0x17) in per_family_init()
3765 pvt->ops = &umc_ops; in per_family_init()
3767 pvt->ops = &dct_ops; in per_family_init()
3769 switch (pvt->fam) { in per_family_init()
3771 pvt->ctl_name = (pvt->ext_model >= K8_REV_F) ? in per_family_init()
3773 pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP; in per_family_init()
3774 pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL; in per_family_init()
3775 pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow; in per_family_init()
3776 pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; in per_family_init()
3780 pvt->ctl_name = "F10h"; in per_family_init()
3781 pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP; in per_family_init()
3782 pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM; in per_family_init()
3783 pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; in per_family_init()
3787 switch (pvt->model) { in per_family_init()
3789 pvt->ctl_name = "F15h_M30h"; in per_family_init()
3790 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; in per_family_init()
3791 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2; in per_family_init()
3794 pvt->ctl_name = "F15h_M60h"; in per_family_init()
3795 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; in per_family_init()
3796 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2; in per_family_init()
3797 pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select; in per_family_init()
3803 pvt->ctl_name = "F15h"; in per_family_init()
3804 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1; in per_family_init()
3805 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2; in per_family_init()
3806 pvt->ops->dbam_to_cs = f15_dbam_to_chip_select; in per_family_init()
3812 switch (pvt->model) { in per_family_init()
3814 pvt->ctl_name = "F16h_M30h"; in per_family_init()
3815 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1; in per_family_init()
3816 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2; in per_family_init()
3819 pvt->ctl_name = "F16h"; in per_family_init()
3820 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1; in per_family_init()
3821 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2; in per_family_init()
3827 switch (pvt->model) { in per_family_init()
3829 pvt->ctl_name = "F17h_M10h"; in per_family_init()
3832 pvt->ctl_name = "F17h_M30h"; in per_family_init()
3833 pvt->max_mcs = 8; in per_family_init()
3836 pvt->ctl_name = "F17h_M60h"; in per_family_init()
3839 pvt->ctl_name = "F17h_M70h"; in per_family_init()
3842 pvt->ctl_name = "F17h"; in per_family_init()
3848 pvt->ctl_name = "F18h"; in per_family_init()
3852 switch (pvt->model) { in per_family_init()
3854 pvt->ctl_name = "F19h"; in per_family_init()
3855 pvt->max_mcs = 8; in per_family_init()
3858 pvt->ctl_name = "F19h_M10h"; in per_family_init()
3859 pvt->max_mcs = 12; in per_family_init()
3860 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3863 pvt->ctl_name = "F19h_M20h"; in per_family_init()
3866 if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) { in per_family_init()
3867 pvt->ctl_name = "MI200"; in per_family_init()
3868 pvt->max_mcs = 4; in per_family_init()
3869 pvt->dram_type = MEM_HBM2; in per_family_init()
3870 pvt->gpu_umc_base = 0x50000; in per_family_init()
3871 pvt->ops = &gpu_ops; in per_family_init()
3873 pvt->ctl_name = "F19h_M30h"; in per_family_init()
3874 pvt->max_mcs = 8; in per_family_init()
3878 pvt->ctl_name = "F19h_M50h"; in per_family_init()
3881 pvt->ctl_name = "F19h_M60h"; in per_family_init()
3882 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3885 pvt->ctl_name = "F19h_M70h"; in per_family_init()
3886 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3889 pvt->ctl_name = "F19h_M90h"; in per_family_init()
3890 pvt->max_mcs = 4; in per_family_init()
3891 pvt->dram_type = MEM_HBM3; in per_family_init()
3892 pvt->gpu_umc_base = 0x90000; in per_family_init()
3893 pvt->ops = &gpu_ops; in per_family_init()
3896 pvt->ctl_name = "F19h_MA0h"; in per_family_init()
3897 pvt->max_mcs = 12; in per_family_init()
3898 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3904 switch (pvt->model) { in per_family_init()
3906 pvt->ctl_name = "F1Ah"; in per_family_init()
3907 pvt->max_mcs = 12; in per_family_init()
3908 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3911 pvt->ctl_name = "F1Ah_M40h"; in per_family_init()
3912 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3937 static unsigned int get_layer_size(struct amd64_pvt *pvt, u8 layer) in get_layer_size() argument
3939 bool is_gpu = (pvt->ops == &gpu_ops); in get_layer_size()
3942 return is_gpu ? pvt->max_mcs in get_layer_size()
3943 : pvt->csels[0].b_cnt; in get_layer_size()
3945 return is_gpu ? pvt->csels[0].b_cnt in get_layer_size()
3946 : pvt->max_mcs; in get_layer_size()
3949 static int init_one_instance(struct amd64_pvt *pvt) in init_one_instance() argument
3956 layers[0].size = get_layer_size(pvt, 0); in init_one_instance()
3959 layers[1].size = get_layer_size(pvt, 1); in init_one_instance()
3962 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
3966 mci->pvt_info = pvt; in init_one_instance()
3967 mci->pdev = &pvt->F3->dev; in init_one_instance()
3969 pvt->ops->setup_mci_misc_attrs(mci); in init_one_instance()
3981 static bool instance_has_memory(struct amd64_pvt *pvt) in instance_has_memory() argument
3986 for (dct = 0; dct < pvt->max_mcs; dct++) { in instance_has_memory()
3987 for_each_chip_select(cs, dct, pvt) in instance_has_memory()
3988 cs_enabled |= csrow_enabled(cs, dct, pvt); in instance_has_memory()
3997 struct amd64_pvt *pvt = NULL; in probe_one_instance() local
4008 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); in probe_one_instance()
4009 if (!pvt) in probe_one_instance()
4012 pvt->mc_node_id = nid; in probe_one_instance()
4013 pvt->F3 = F3; in probe_one_instance()
4015 ret = per_family_init(pvt); in probe_one_instance()
4019 ret = pvt->ops->hw_info_get(pvt); in probe_one_instance()
4024 if (!instance_has_memory(pvt)) { in probe_one_instance()
4029 if (!pvt->ops->ecc_enabled(pvt)) { in probe_one_instance()
4045 ret = init_one_instance(pvt); in probe_one_instance()
4055 amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); in probe_one_instance()
4058 pvt->ops->dump_misc_regs(pvt); in probe_one_instance()
4063 hw_info_put(pvt); in probe_one_instance()
4064 kfree(pvt); in probe_one_instance()
4079 struct amd64_pvt *pvt; in remove_one_instance() local
4086 pvt = mci->pvt_info; in remove_one_instance()
4096 hw_info_put(pvt); in remove_one_instance()
4097 kfree(pvt); in remove_one_instance()