11 #include <linux/edac.h>
77 /*********************** EDAC Memory Controller Functions ****************/
79 /* The SDRAM controller uses the EDAC Memory Controller framework.       */
225 	{ .compatible = "altr,sdram-edac", .data = &c5_data},
226 	{ .compatible = "altr,sdram-edac-a10", .data = &a10_data},
451 		    "EDAC Probe Failed; Error %d\n", res);  in altr_sdram_probe()
466  * If you want to suspend, need to disable EDAC by removing it
472 	pr_err("Suspend not allowed when EDAC is enabled.\n");  in altr_sdram_prepare()
498 /************************* EDAC Parent Probe *************************/
524 /************************* EDAC Device Functions *************************/
527  * EDAC Device Functions (shared between various IPs).
528  * The discrete memories use the EDAC Device framework. The probe
530  * so they are shared. The memory allocation and freeing for EDAC
700  *	This is a generic EDAC device driver that will support
743 			    "%s: Unable to allocate EDAC device\n", ecc_name);  in altr_edac_device_probe()
759 	/* Get driver specific data for this EDAC device */  in altr_edac_device_probe()
801 		    "%s:Error setting up EDAC device: %d\n", ecc_name, res);  in altr_edac_device_probe()
1068 /*********************** SDRAM EDAC Device Functions *********************/
1124 /*********************** OCRAM EDAC Device Functions *********************/
1222 /********************* L2 Cache EDAC Device Functions ********************/
1282 		regmap_write(dci->edac->ecc_mgr_map,  in altr_edac_a10_l2_irq()
1289 		regmap_write(dci->edac->ecc_mgr_map,  in altr_edac_a10_l2_irq()
1509 	/* Create the PortB EDAC device */  in altr_portb_setup()
1515 			    "%s: Unable to allocate PortB EDAC device\n",  in altr_portb_setup()
1520 	/* Initialize the PortB EDAC device structure from PortA structure */  in altr_portb_setup()
1596 	list_add(&altdev->next, &altdev->edac->a10_ecc_devices);  in altr_portb_setup()
1606 		    "%s:Error setting up EDAC device: %d\n", ecc_name, rc);  in altr_portb_setup()
1690 /********************* Arria10 EDAC Device Functions *************************/
1719 	{ .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1726  * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1760  * The Stratix10 EDAC Error Injection Functions differ from Arria10
1825 	struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);  in altr_edac_a10_irq_handler()  local
1830 	dberr = (irq == edac->db_irq) ? 1 : 0;  in altr_edac_a10_irq_handler()
1836 	regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);  in altr_edac_a10_irq_handler()
1840 		generic_handle_domain_irq(edac->domain, dberr * 32 + bit);  in altr_edac_a10_irq_handler()
1851 	if (of_device_is_compatible(np, "altr,sdram-edac-s10"))  in validate_parent_available()
1879 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,  in altr_edac_a10_device_add()  argument
1895 	/* Get driver specific data for this EDAC device */  in altr_edac_a10_device_add()
1903 	if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))  in altr_edac_a10_device_add()
1906 	if (of_device_is_compatible(np, "altr,sdram-edac-s10"))  in altr_edac_a10_device_add()
1923 			    "%s: Unable to allocate EDAC device\n", ecc_name);  in altr_edac_a10_device_add()
1929 	dci->dev = edac->dev;  in altr_edac_a10_device_add()
1932 	altdev->edac = edac;  in altr_edac_a10_device_add()
1935 	altdev->ddev = *edac->dev;  in altr_edac_a10_device_add()
1941 	altdev->base = devm_ioremap_resource(edac->dev, &res);  in altr_edac_a10_device_add()
1960 	rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,  in altr_edac_a10_device_add()
1983 	rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,  in altr_edac_a10_device_add()
1994 		dev_err(edac->dev, "edac_device_add_device failed\n");  in altr_edac_a10_device_add()
2001 	list_add(&altdev->next, &edac->a10_ecc_devices);  in altr_edac_a10_device_add()
2003 	devres_remove_group(edac->dev, altr_edac_a10_device_add);  in altr_edac_a10_device_add()
2010 	devres_release_group(edac->dev, NULL);  in altr_edac_a10_device_add()
2012 		    "%s:Error setting up EDAC device: %d\n", ecc_name, rc);  in altr_edac_a10_device_add()
2019 	struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);  in a10_eccmgr_irq_mask()  local
2021 	regmap_write(edac->ecc_mgr_map,	A10_SYSMGR_ECC_INTMASK_SET_OFST,  in a10_eccmgr_irq_mask()
2027 	struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);  in a10_eccmgr_irq_unmask()  local
2029 	regmap_write(edac->ecc_mgr_map,	A10_SYSMGR_ECC_INTMASK_CLR_OFST,  in a10_eccmgr_irq_unmask()
2036 	struct altr_arria10_edac *edac = d->host_data;  in a10_eccmgr_irqdomain_map()  local
2038 	irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);  in a10_eccmgr_irqdomain_map()
2039 	irq_set_chip_data(irq, edac);  in a10_eccmgr_irqdomain_map()
2050 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2064 	struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);  in s10_edac_dberr_handler()  local
2067 	regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,  in s10_edac_dberr_handler()
2069 	regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);  in s10_edac_dberr_handler()
2076 		list_for_each(position, &edac->a10_ecc_devices) {  in s10_edac_dberr_handler()
2085 			regmap_write(edac->ecc_mgr_map,  in s10_edac_dberr_handler()
2088 				    "EDAC: [Fatal DBE on %s @ 0x%08X]\n",  in s10_edac_dberr_handler()
2102 /****************** Arria 10 EDAC Probe Function *********************/
2105 	struct altr_arria10_edac *edac;  in altr_edac_a10_probe()  local
2108 	edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);  in altr_edac_a10_probe()
2109 	if (!edac)  in altr_edac_a10_probe()
2112 	edac->dev = &pdev->dev;  in altr_edac_a10_probe()
2113 	platform_set_drvdata(pdev, edac);  in altr_edac_a10_probe()
2114 	INIT_LIST_HEAD(&edac->a10_ecc_devices);  in altr_edac_a10_probe()
2116 	edac->ecc_mgr_map =  in altr_edac_a10_probe()
2120 	if (IS_ERR(edac->ecc_mgr_map)) {  in altr_edac_a10_probe()
2123 		return PTR_ERR(edac->ecc_mgr_map);  in altr_edac_a10_probe()
2127 	regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,  in altr_edac_a10_probe()
2130 	edac->irq_chip.name = pdev->dev.of_node->name;  in altr_edac_a10_probe()
2131 	edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;  in altr_edac_a10_probe()
2132 	edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;  in altr_edac_a10_probe()
2133 	edac->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), 64, &a10_eccmgr_ic_ops,  in altr_edac_a10_probe()
2134 						edac);  in altr_edac_a10_probe()
2135 	if (!edac->domain) {  in altr_edac_a10_probe()
2140 	edac->sb_irq = platform_get_irq(pdev, 0);  in altr_edac_a10_probe()
2141 	if (edac->sb_irq < 0)  in altr_edac_a10_probe()
2142 		return edac->sb_irq;  in altr_edac_a10_probe()
2144 	irq_set_chained_handler_and_data(edac->sb_irq,  in altr_edac_a10_probe()
2146 					 edac);  in altr_edac_a10_probe()
2152 		edac->panic_notifier.notifier_call = s10_edac_dberr_handler;  in altr_edac_a10_probe()
2154 					       &edac->panic_notifier);  in altr_edac_a10_probe()
2157 		regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,  in altr_edac_a10_probe()
2160 			regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,  in altr_edac_a10_probe()
2166 			regmap_write(edac->ecc_mgr_map,  in altr_edac_a10_probe()
2168 			regmap_write(edac->ecc_mgr_map,  in altr_edac_a10_probe()
2173 	edac->db_irq = platform_get_irq(pdev, 1);  in altr_edac_a10_probe()
2174 	if (edac->db_irq < 0)  in altr_edac_a10_probe()
2175 		return edac->db_irq;  in altr_edac_a10_probe()
2177 	irq_set_chained_handler_and_data(edac->db_irq,  in altr_edac_a10_probe()
2178 					 altr_edac_a10_irq_handler, edac);  in altr_edac_a10_probe()
2186 			altr_edac_a10_device_add(edac, child);  in altr_edac_a10_probe()
2189 		else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))  in altr_edac_a10_probe()
2216 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");