Lines Matching +full:0 +full:- +full:indexed
1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * 25 19 18 16 15 7 6 0
13 * +------------------------------------------+
15 * +------------------------------------------+
17 * page_offset ... <0x00..0x7F>
20 * max_offset .... maximal offset for indexed registers
21 * (for non-indexed regs max_offset == page_offset)
24 #define ZL_REG_OFFSET_MASK GENMASK(6, 0)
28 #define ZL_REG_ADDR_MASK GENMASK(15, 0)
37 * ZL_REG_IDX - define indexed register
53 (_offset) + ((_items) - 1) * (_stride)))
56 * ZL_REG - define simple (non-indexed) register
64 ZL_REG_IDX(0, _page, _offset, _size, 1, 0)
67 * Register Page 0, General
70 #define ZL_REG_INFO ZL_REG(0, 0x00, 1)
73 #define ZL_REG_ID ZL_REG(0, 0x01, 2)
74 #define ZL_REG_REVISION ZL_REG(0, 0x03, 2)
75 #define ZL_REG_FW_VER ZL_REG(0, 0x05, 2)
76 #define ZL_REG_CUSTOM_CONFIG_VER ZL_REG(0, 0x07, 4)
78 #define ZL_REG_RESET_STATUS ZL_REG(0, 0x18, 1)
79 #define ZL_REG_RESET_STATUS_RESET BIT(0)
86 ZL_REG_IDX(_idx, 2, 0x02, 1, ZL3073X_NUM_REFS, 1)
87 #define ZL_REF_MON_STATUS_OK 0 /* all bits zeroed */
90 ZL_REG_IDX(_idx, 2, 0x10, 1, ZL3073X_MAX_CHANNELS, 1)
91 #define ZL_DPLL_MON_STATUS_STATE GENMASK(1, 0)
92 #define ZL_DPLL_MON_STATUS_STATE_ACQUIRING 0
98 ZL_REG_IDX(_idx, 2, 0x30, 1, ZL3073X_MAX_CHANNELS, 1)
99 #define ZL_DPLL_REFSEL_STATUS_REFSEL GENMASK(3, 0)
104 ZL_REG_IDX(_idx, 2, 0x44, 4, ZL3073X_NUM_REFS, 4)
110 #define ZL_REG_REF_PHASE_ERR_READ_RQST ZL_REG(4, 0x0f, 1)
111 #define ZL_REF_PHASE_ERR_READ_RQST_RD BIT(0)
113 #define ZL_REG_REF_FREQ_MEAS_CTRL ZL_REG(4, 0x1c, 1)
114 #define ZL_REF_FREQ_MEAS_CTRL GENMASK(1, 0)
119 #define ZL_REG_REF_FREQ_MEAS_MASK_3_0 ZL_REG(4, 0x1d, 1)
122 #define ZL_REG_REF_FREQ_MEAS_MASK_4 ZL_REG(4, 0x1e, 1)
123 #define ZL_REF_FREQ_MEAS_MASK_4(_ref) BIT((_ref) - 8)
125 #define ZL_REG_DPLL_MEAS_REF_FREQ_CTRL ZL_REG(4, 0x1f, 1)
126 #define ZL_DPLL_MEAS_REF_FREQ_CTRL_EN BIT(0)
130 ZL_REG_IDX(_idx, 4, 0x20, 6, ZL3073X_NUM_REFS, 6)
137 ZL_REG_IDX(_idx, 5, 0x04, 1, ZL3073X_MAX_CHANNELS, 4)
138 #define ZL_DPLL_MODE_REFSEL_MODE GENMASK(2, 0)
139 #define ZL_DPLL_MODE_REFSEL_MODE_FREERUN 0
146 #define ZL_REG_DPLL_MEAS_CTRL ZL_REG(5, 0x50, 1)
147 #define ZL_DPLL_MEAS_CTRL_EN BIT(0)
150 #define ZL_REG_DPLL_MEAS_IDX ZL_REG(5, 0x51, 1)
151 #define ZL_DPLL_MEAS_IDX GENMASK(2, 0)
153 #define ZL_REG_DPLL_PHASE_ERR_READ_MASK ZL_REG(5, 0x54, 1)
156 ZL_REG_IDX(_idx, 5, 0x55, 6, ZL3073X_MAX_CHANNELS, 6)
163 ZL_REG_IDX(_idx, 9, 0x00, 1, ZL3073X_NUM_SYNTHS, 1)
164 #define ZL_SYNTH_CTRL_EN BIT(0)
167 #define ZL_REG_SYNTH_PHASE_SHIFT_CTRL ZL_REG(9, 0x1e, 1)
168 #define ZL_REG_SYNTH_PHASE_SHIFT_MASK ZL_REG(9, 0x1f, 1)
169 #define ZL_REG_SYNTH_PHASE_SHIFT_INTVL ZL_REG(9, 0x20, 1)
170 #define ZL_REG_SYNTH_PHASE_SHIFT_DATA ZL_REG(9, 0x21, 2)
173 ZL_REG_IDX(_idx, 9, 0x28, 1, ZL3073X_NUM_OUTS, 1)
174 #define ZL_OUTPUT_CTRL_EN BIT(0)
181 #define ZL_REG_REF_MB_MASK ZL_REG(10, 0x02, 2)
183 #define ZL_REG_REF_MB_SEM ZL_REG(10, 0x04, 1)
184 #define ZL_REF_MB_SEM_WR BIT(0)
187 #define ZL_REG_REF_FREQ_BASE ZL_REG(10, 0x05, 2)
188 #define ZL_REG_REF_FREQ_MULT ZL_REG(10, 0x07, 2)
189 #define ZL_REG_REF_RATIO_M ZL_REG(10, 0x09, 2)
190 #define ZL_REG_REF_RATIO_N ZL_REG(10, 0x0b, 2)
192 #define ZL_REG_REF_CONFIG ZL_REG(10, 0x0d, 1)
193 #define ZL_REF_CONFIG_ENABLE BIT(0)
196 #define ZL_REG_REF_PHASE_OFFSET_COMP ZL_REG(10, 0x28, 6)
198 #define ZL_REG_REF_SYNC_CTRL ZL_REG(10, 0x2e, 1)
199 #define ZL_REF_SYNC_CTRL_MODE GENMASK(2, 0)
200 #define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF 0
203 #define ZL_REG_REF_ESYNC_DIV ZL_REG(10, 0x30, 4)
204 #define ZL_REF_ESYNC_DIV_1HZ 0
210 #define ZL_REG_DPLL_MB_MASK ZL_REG(12, 0x02, 2)
212 #define ZL_REG_DPLL_MB_SEM ZL_REG(12, 0x04, 1)
213 #define ZL_DPLL_MB_SEM_WR BIT(0)
217 ZL_REG_IDX(_idx, 12, 0x52, 1, ZL3073X_NUM_REFS / 2, 1)
218 #define ZL_DPLL_REF_PRIO_REF_P GENMASK(3, 0)
227 #define ZL_REG_SYNTH_MB_MASK ZL_REG(13, 0x02, 2)
229 #define ZL_REG_SYNTH_MB_SEM ZL_REG(13, 0x04, 1)
230 #define ZL_SYNTH_MB_SEM_WR BIT(0)
233 #define ZL_REG_SYNTH_FREQ_BASE ZL_REG(13, 0x06, 2)
234 #define ZL_REG_SYNTH_FREQ_MULT ZL_REG(13, 0x08, 4)
235 #define ZL_REG_SYNTH_FREQ_M ZL_REG(13, 0x0c, 2)
236 #define ZL_REG_SYNTH_FREQ_N ZL_REG(13, 0x0e, 2)
241 #define ZL_REG_OUTPUT_MB_MASK ZL_REG(14, 0x02, 2)
243 #define ZL_REG_OUTPUT_MB_SEM ZL_REG(14, 0x04, 1)
244 #define ZL_OUTPUT_MB_SEM_WR BIT(0)
247 #define ZL_REG_OUTPUT_MODE ZL_REG(14, 0x05, 1)
248 #define ZL_OUTPUT_MODE_CLOCK_TYPE GENMASK(2, 0)
249 #define ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL 0
252 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DISABLED 0
263 #define ZL_REG_OUTPUT_DIV ZL_REG(14, 0x0c, 4)
264 #define ZL_REG_OUTPUT_WIDTH ZL_REG(14, 0x10, 4)
265 #define ZL_REG_OUTPUT_ESYNC_PERIOD ZL_REG(14, 0x14, 4)
266 #define ZL_REG_OUTPUT_ESYNC_WIDTH ZL_REG(14, 0x18, 4)
267 #define ZL_REG_OUTPUT_PHASE_COMP ZL_REG(14, 0x20, 4)
270 * Register Page 255 - HW registers access
272 #define ZL_REG_HWREG_OP ZL_REG(0xff, 0x00, 1)
273 #define ZL_HWREG_OP_WRITE 0x28
274 #define ZL_HWREG_OP_READ 0x29
277 #define ZL_REG_HWREG_ADDR ZL_REG(0xff, 0x04, 4)
278 #define ZL_REG_HWREG_WRITE_DATA ZL_REG(0xff, 0x08, 4)
279 #define ZL_REG_HWREG_READ_DATA ZL_REG(0xff, 0x0c, 4)
284 #define ZL_REG_FLASH_HASH ZL_REG(0, 0x78, 4)
285 #define ZL_REG_FLASH_FAMILY ZL_REG(0, 0x7c, 1)
286 #define ZL_REG_FLASH_RELEASE ZL_REG(0, 0x7d, 1)
288 #define ZL_REG_HOST_CONTROL ZL_REG(1, 0x02, 1)
289 #define ZL_HOST_CONTROL_ENABLE BIT(0)
291 #define ZL_REG_IMAGE_START_ADDR ZL_REG(1, 0x04, 4)
292 #define ZL_REG_IMAGE_SIZE ZL_REG(1, 0x08, 4)
293 #define ZL_REG_FLASH_INDEX_READ ZL_REG(1, 0x0c, 4)
294 #define ZL_REG_FLASH_INDEX_WRITE ZL_REG(1, 0x10, 4)
295 #define ZL_REG_FILL_PATTERN ZL_REG(1, 0x14, 4)
297 #define ZL_REG_WRITE_FLASH ZL_REG(1, 0x18, 1)
298 #define ZL_WRITE_FLASH_OP GENMASK(2, 0)
299 #define ZL_WRITE_FLASH_OP_DONE 0x0
300 #define ZL_WRITE_FLASH_OP_SECTORS 0x2
301 #define ZL_WRITE_FLASH_OP_PAGE 0x3
302 #define ZL_WRITE_FLASH_OP_COPY_PAGE 0x4
304 #define ZL_REG_FLASH_INFO ZL_REG(2, 0x00, 1)
305 #define ZL_FLASH_INFO_SECTOR_SIZE GENMASK(3, 0)
306 #define ZL_FLASH_INFO_SECTOR_4K 0
309 #define ZL_REG_ERROR_COUNT ZL_REG(2, 0x04, 4)
310 #define ZL_REG_ERROR_CAUSE ZL_REG(2, 0x08, 4)
312 #define ZL_REG_OP_STATE ZL_REG(2, 0x14, 1)
313 #define ZL_OP_STATE_NO_COMMAND 0