Lines Matching +full:sense +full:- +full:bitfield +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/bitfield.h>
28 * struct zl3073x_dpll_pin - DPLL pin
65 * zl3073x_dpll_is_input_pin - check if the pin is input one
73 return pin->dir == DPLL_PIN_DIRECTION_INPUT; in zl3073x_dpll_is_input_pin()
77 * zl3073x_dpll_is_p_pin - check if the pin is P-pin
80 * Return: true if the pin is P-pin, false if it is N-pin
85 return zl3073x_is_p_pin(pin->id); in zl3073x_dpll_is_p_pin()
96 *direction = pin->dir; in zl3073x_dpll_pin_direction_get()
102 * zl3073x_dpll_input_ref_frequency_get - get input reference frequency
115 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_ref_frequency_get()
119 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_ref_frequency_get()
143 dev_err(zldev->dev, in zl3073x_dpll_input_ref_frequency_get()
146 return -EINVAL; in zl3073x_dpll_input_ref_frequency_get()
164 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_esync_get()
171 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_esync_get()
172 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, pin->id, &ref_freq); in zl3073x_dpll_input_pin_esync_get()
176 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_esync_get()
198 esync->freq = (esync_div == ZL_REF_ESYNC_DIV_1HZ) ? 1 : 0; in zl3073x_dpll_input_pin_esync_get()
199 esync->pulse = 25; in zl3073x_dpll_input_pin_esync_get()
202 esync->freq = 0; in zl3073x_dpll_input_pin_esync_get()
203 esync->pulse = 0; in zl3073x_dpll_input_pin_esync_get()
210 if (pin->esync_control && ref_freq > 1) { in zl3073x_dpll_input_pin_esync_get()
211 esync->range = esync_freq_ranges; in zl3073x_dpll_input_pin_esync_get()
212 esync->range_num = ARRAY_SIZE(esync_freq_ranges); in zl3073x_dpll_input_pin_esync_get()
214 esync->range = NULL; in zl3073x_dpll_input_pin_esync_get()
215 esync->range_num = 0; in zl3073x_dpll_input_pin_esync_get()
229 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_esync_set()
234 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_esync_set()
237 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_esync_set()
282 *ffo = pin->freq_offset; in zl3073x_dpll_input_pin_ffo_get()
301 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_frequency_get()
317 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_frequency_set()
328 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_frequency_set()
331 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_frequency_set()
355 * zl3073x_dpll_selected_ref_get - get currently selected reference
367 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_selected_ref_get()
371 switch (zldpll->refsel_mode) { in zl3073x_dpll_selected_ref_get()
375 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), in zl3073x_dpll_selected_ref_get()
391 *ref = zldpll->forced_ref; in zl3073x_dpll_selected_ref_get()
403 * zl3073x_dpll_selected_ref_set - select reference in manual mode
415 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_selected_ref_set()
419 mode = zldpll->refsel_mode; in zl3073x_dpll_selected_ref_set()
425 switch (zldpll->lock_status) { in zl3073x_dpll_selected_ref_set()
437 ref = zldpll->forced_ref; in zl3073x_dpll_selected_ref_set()
438 } else if (ref == zldpll->forced_ref) { in zl3073x_dpll_selected_ref_set()
439 /* No register update - same mode and same ref */ in zl3073x_dpll_selected_ref_set()
447 /* No register update - keep current mode */ in zl3073x_dpll_selected_ref_set()
457 return -EOPNOTSUPP; in zl3073x_dpll_selected_ref_set()
465 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), in zl3073x_dpll_selected_ref_set()
471 zldpll->refsel_mode = mode; in zl3073x_dpll_selected_ref_set()
472 zldpll->forced_ref = ref; in zl3073x_dpll_selected_ref_set()
478 * zl3073x_dpll_connected_ref_get - get currently connected reference
490 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_connected_ref_get()
523 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_phase_offset_get()
537 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_phase_offset_get()
538 if (!zldpll->phase_monitor && ref != conn_ref) { in zl3073x_dpll_input_pin_phase_offset_get()
556 ref_phase = pin->phase_offset; in zl3073x_dpll_input_pin_phase_offset_get()
582 ref_phase -= conn_period * div_factor; in zl3073x_dpll_input_pin_phase_offset_get()
600 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_phase_adjust_get()
606 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_phase_adjust_get()
609 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_phase_adjust_get()
626 *phase_adjust = (s32)-phase_comp; in zl3073x_dpll_input_pin_phase_adjust_get()
640 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_phase_adjust_set()
649 phase_comp = -phase_adjust; in zl3073x_dpll_input_pin_phase_adjust_set()
651 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_phase_adjust_set()
654 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_phase_adjust_set()
671 * zl3073x_dpll_ref_prio_get - get priority for given input pin
683 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_ref_prio_get()
684 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_ref_prio_get()
688 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_ref_prio_get()
692 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); in zl3073x_dpll_ref_prio_get()
696 /* Read reference priority - one value for P&N pins (4 bits/pin) */ in zl3073x_dpll_ref_prio_get()
697 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_ref_prio_get()
713 * zl3073x_dpll_ref_prio_set - set priority for given input pin
724 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_ref_prio_set()
725 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_ref_prio_set()
729 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_ref_prio_set()
733 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); in zl3073x_dpll_ref_prio_set()
737 /* Read reference priority - one value shared between P&N pins */ in zl3073x_dpll_ref_prio_set()
738 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_ref_prio_set()
759 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); in zl3073x_dpll_ref_prio_set()
763 * zl3073x_dpll_ref_state_get - get status for given input pin
776 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_ref_state_get()
777 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_ref_state_get()
781 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_ref_state_get()
797 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && in zl3073x_dpll_ref_state_get()
798 pin->selectable) { in zl3073x_dpll_ref_state_get()
846 switch (zldpll->refsel_mode) { in zl3073x_dpll_input_pin_state_on_dpll_set()
852 new_ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_state_on_dpll_set()
859 return -EINVAL; in zl3073x_dpll_input_pin_state_on_dpll_set()
867 if (pin->selectable) in zl3073x_dpll_input_pin_state_on_dpll_set()
871 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); in zl3073x_dpll_input_pin_state_on_dpll_set()
876 pin->selectable = true; in zl3073x_dpll_input_pin_state_on_dpll_set()
878 if (!pin->selectable) in zl3073x_dpll_input_pin_state_on_dpll_set()
887 /* Mark pin as non-selectable */ in zl3073x_dpll_input_pin_state_on_dpll_set()
888 pin->selectable = false; in zl3073x_dpll_input_pin_state_on_dpll_set()
892 return -EINVAL; in zl3073x_dpll_input_pin_state_on_dpll_set()
900 rc = -EOPNOTSUPP; in zl3073x_dpll_input_pin_state_on_dpll_set()
914 *prio = pin->prio; in zl3073x_dpll_input_pin_prio_get()
928 return -EINVAL; in zl3073x_dpll_input_pin_prio_set()
931 if (pin->selectable) { in zl3073x_dpll_input_pin_prio_set()
938 pin->prio = prio; in zl3073x_dpll_input_pin_prio_set()
952 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_esync_get()
954 struct device *dev = zldev->dev; in zl3073x_dpll_output_pin_esync_get()
962 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_esync_get()
964 /* If N-division is enabled, esync is not supported. The register used in zl3073x_dpll_output_pin_esync_get()
965 * for N-division is also used for the esync divider so both cannot in zl3073x_dpll_output_pin_esync_get()
971 return -EOPNOTSUPP; in zl3073x_dpll_output_pin_esync_get()
976 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_esync_get()
998 return -EINVAL; in zl3073x_dpll_output_pin_esync_get()
1010 esync->freq = 0; in zl3073x_dpll_output_pin_esync_get()
1011 esync->pulse = 0; in zl3073x_dpll_output_pin_esync_get()
1025 return -EINVAL; in zl3073x_dpll_output_pin_esync_get()
1028 /* Get esync pulse width in units of half synth cycles */ in zl3073x_dpll_output_pin_esync_get()
1034 esync->freq = synth_freq / output_div / esync_period; in zl3073x_dpll_output_pin_esync_get()
1036 /* By comparing the esync_pulse_width to the half of the pulse width in zl3073x_dpll_output_pin_esync_get()
1038 * Note that half pulse width is in units of half synth cycles, which in zl3073x_dpll_output_pin_esync_get()
1041 esync->pulse = (50 * esync_width) / output_div; in zl3073x_dpll_output_pin_esync_get()
1047 if (pin->esync_control && (synth_freq / output_div) > 1) { in zl3073x_dpll_output_pin_esync_get()
1048 esync->range = esync_freq_ranges; in zl3073x_dpll_output_pin_esync_get()
1049 esync->range_num = ARRAY_SIZE(esync_freq_ranges); in zl3073x_dpll_output_pin_esync_get()
1051 esync->range = NULL; in zl3073x_dpll_output_pin_esync_get()
1052 esync->range_num = 0; in zl3073x_dpll_output_pin_esync_get()
1067 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_esync_set()
1073 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_esync_set()
1075 /* If N-division is enabled, esync is not supported. The register used in zl3073x_dpll_output_pin_esync_set()
1076 * for N-division is also used for the esync divider so both cannot in zl3073x_dpll_output_pin_esync_set()
1082 return -EOPNOTSUPP; in zl3073x_dpll_output_pin_esync_set()
1087 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_esync_set()
1129 dev_err(zldev->dev, in zl3073x_dpll_output_pin_esync_set()
1131 return -EINVAL; in zl3073x_dpll_output_pin_esync_set()
1141 * the output_div. To get the supported esync pulse width of 25% of the in zl3073x_dpll_output_pin_esync_set()
1165 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_frequency_get()
1167 struct device *dev = zldev->dev; in zl3073x_dpll_output_pin_frequency_get()
1172 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_frequency_get()
1176 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_frequency_get()
1192 return -EINVAL; in zl3073x_dpll_output_pin_frequency_get()
1205 /* For P-pin the resulting frequency is computed as in zl3073x_dpll_output_pin_frequency_get()
1211 /* For N-pin we have to divide additionally by in zl3073x_dpll_output_pin_frequency_get()
1213 * register that is used as N-pin divisor for these in zl3073x_dpll_output_pin_frequency_get()
1223 /* Check N-pin divisor for zero */ in zl3073x_dpll_output_pin_frequency_get()
1226 "Zero N-pin divisor for output %u got from device\n", in zl3073x_dpll_output_pin_frequency_get()
1228 return -EINVAL; in zl3073x_dpll_output_pin_frequency_get()
1231 /* Compute final divisor for N-pin */ in zl3073x_dpll_output_pin_frequency_get()
1254 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_frequency_set()
1256 struct device *dev = zldev->dev; in zl3073x_dpll_output_pin_frequency_set()
1263 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_frequency_set()
1271 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_frequency_set()
1282 /* For non N-divided signal formats the frequency is computed in zl3073x_dpll_output_pin_frequency_set()
1289 /* For 50/50 duty cycle the divisor is equal to width */ in zl3073x_dpll_output_pin_frequency_set()
1300 /* For N-divided signal format get current divisor */ in zl3073x_dpll_output_pin_frequency_set()
1309 return -EINVAL; in zl3073x_dpll_output_pin_frequency_set()
1312 /* Get N-pin divisor (shares the same register with esync */ in zl3073x_dpll_output_pin_frequency_set()
1317 /* Check N-pin divisor for zero */ in zl3073x_dpll_output_pin_frequency_set()
1320 "Zero N-pin divisor for output %u got from device\n", in zl3073x_dpll_output_pin_frequency_set()
1322 return -EINVAL; in zl3073x_dpll_output_pin_frequency_set()
1325 /* Compute current output frequency for P-pin */ in zl3073x_dpll_output_pin_frequency_set()
1328 /* Compute current N-pin frequency */ in zl3073x_dpll_output_pin_frequency_set()
1332 /* We are going to change output frequency for P-pin but in zl3073x_dpll_output_pin_frequency_set()
1333 * if the requested frequency is less than current N-pin in zl3073x_dpll_output_pin_frequency_set()
1335 * to compute N-pin divisor to keep its frequency unchanged. in zl3073x_dpll_output_pin_frequency_set()
1338 return -EINVAL; in zl3073x_dpll_output_pin_frequency_set()
1345 /* For 50/50 duty cycle the divisor is equal to width */ in zl3073x_dpll_output_pin_frequency_set()
1350 /* Compute new divisor for N-pin */ in zl3073x_dpll_output_pin_frequency_set()
1353 /* We are going to change frequency of N-pin but if in zl3073x_dpll_output_pin_frequency_set()
1354 * the requested freq is greater or equal than freq of P-pin in zl3073x_dpll_output_pin_frequency_set()
1355 * in the output pair we cannot compute divisor for the N-pin. in zl3073x_dpll_output_pin_frequency_set()
1359 return -EINVAL; in zl3073x_dpll_output_pin_frequency_set()
1361 /* Compute new divisor for N-pin */ in zl3073x_dpll_output_pin_frequency_set()
1365 /* Update divisor for the N-pin */ in zl3073x_dpll_output_pin_frequency_set()
1370 /* For 50/50 duty cycle the divisor is equal to width */ in zl3073x_dpll_output_pin_frequency_set()
1389 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_phase_adjust_get()
1396 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_phase_adjust_get()
1402 dev_err(zldev->dev, "Got zero synth frequency for output %u\n", in zl3073x_dpll_output_pin_phase_adjust_get()
1404 return -EINVAL; in zl3073x_dpll_output_pin_phase_adjust_get()
1407 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_phase_adjust_get()
1424 *phase_adjust = -phase_comp; in zl3073x_dpll_output_pin_phase_adjust_get()
1438 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_phase_adjust_set()
1446 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_phase_adjust_set()
1461 return -EINVAL; in zl3073x_dpll_output_pin_phase_adjust_set()
1468 phase_adjust = -phase_adjust; in zl3073x_dpll_output_pin_phase_adjust_set()
1470 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_phase_adjust_set()
1509 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_lock_status_get()
1513 switch (zldpll->refsel_mode) { in zl3073x_dpll_lock_status_get()
1525 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), in zl3073x_dpll_lock_status_get()
1543 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", in zl3073x_dpll_lock_status_get()
1558 switch (zldpll->refsel_mode) { in zl3073x_dpll_mode_get()
1573 return -EINVAL; in zl3073x_dpll_mode_get()
1586 *factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev); in zl3073x_dpll_phase_offset_avg_factor_get()
1597 dpll_device_change_ntf(zldpll->dpll_dev); in zl3073x_dpll_change_work()
1611 return -EINVAL; in zl3073x_dpll_phase_offset_avg_factor_set()
1614 rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor); in zl3073x_dpll_phase_offset_avg_factor_set()
1624 list_for_each_entry(item, &zldpll->dev->dplls, list) { in zl3073x_dpll_phase_offset_avg_factor_set()
1626 schedule_work(&item->change_work); in zl3073x_dpll_phase_offset_avg_factor_set()
1640 if (zldpll->phase_monitor) in zl3073x_dpll_phase_offset_monitor_get()
1656 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); in zl3073x_dpll_phase_offset_monitor_set()
1698 * zl3073x_dpll_pin_alloc - allocate DPLL pin
1716 return ERR_PTR(-ENOMEM); in zl3073x_dpll_pin_alloc()
1718 pin->dpll = zldpll; in zl3073x_dpll_pin_alloc()
1719 pin->dir = dir; in zl3073x_dpll_pin_alloc()
1720 pin->id = id; in zl3073x_dpll_pin_alloc()
1726 * zl3073x_dpll_pin_free - deallocate DPLL pin
1734 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); in zl3073x_dpll_pin_free()
1740 * zl3073x_dpll_pin_register - register DPLL pin
1744 * Registers given DPLL pin into DPLL sub-system.
1751 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_pin_register()
1757 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); in zl3073x_dpll_pin_register()
1762 strscpy(pin->label, props->package_label); in zl3073x_dpll_pin_register()
1763 pin->esync_control = props->esync_control; in zl3073x_dpll_pin_register()
1766 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); in zl3073x_dpll_pin_register()
1770 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { in zl3073x_dpll_pin_register()
1771 /* Clamp prio to max value & mark pin non-selectable */ in zl3073x_dpll_pin_register()
1772 pin->prio = ZL_DPLL_REF_PRIO_MAX; in zl3073x_dpll_pin_register()
1773 pin->selectable = false; in zl3073x_dpll_pin_register()
1776 pin->selectable = true; in zl3073x_dpll_pin_register()
1781 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, in zl3073x_dpll_pin_register()
1782 &props->dpll_props); in zl3073x_dpll_pin_register()
1783 if (IS_ERR(pin->dpll_pin)) { in zl3073x_dpll_pin_register()
1784 rc = PTR_ERR(pin->dpll_pin); in zl3073x_dpll_pin_register()
1794 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); in zl3073x_dpll_pin_register()
1804 dpll_pin_put(pin->dpll_pin); in zl3073x_dpll_pin_register()
1806 pin->dpll_pin = NULL; in zl3073x_dpll_pin_register()
1814 * zl3073x_dpll_pin_unregister - unregister DPLL pin
1822 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_pin_unregister()
1825 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); in zl3073x_dpll_pin_unregister()
1833 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); in zl3073x_dpll_pin_unregister()
1835 dpll_pin_put(pin->dpll_pin); in zl3073x_dpll_pin_unregister()
1836 pin->dpll_pin = NULL; in zl3073x_dpll_pin_unregister()
1840 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins
1851 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { in zl3073x_dpll_pins_unregister()
1853 list_del(&pin->list); in zl3073x_dpll_pins_unregister()
1859 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable
1866 * differential signal type only P-pin is reported as registrable.
1876 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_pin_is_registrable()
1886 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) in zl3073x_dpll_pin_is_registrable()
1898 if (zl3073x_out_dpll_get(zldev, out) != zldpll->id) { in zl3073x_dpll_pin_is_registrable()
1899 dev_dbg(zldev->dev, in zl3073x_dpll_pin_is_registrable()
1910 /* Skip N-pin if the corresponding input/output is differential */ in zl3073x_dpll_pin_is_registrable()
1912 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", in zl3073x_dpll_pin_is_registrable()
1920 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, in zl3073x_dpll_pin_is_registrable()
1930 * zl3073x_dpll_pins_register - register all registerable DPLL pins
1953 id = index - ZL3073X_NUM_INPUT_PINS; in zl3073x_dpll_pins_register()
1971 list_add(&pin->list, &zldpll->pins); in zl3073x_dpll_pins_register()
1983 * zl3073x_dpll_device_register - register DPLL device
1986 * Registers given DPLL device into DPLL sub-system.
1993 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_device_register()
1998 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), in zl3073x_dpll_device_register()
2004 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, in zl3073x_dpll_device_register()
2006 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, in zl3073x_dpll_device_register()
2009 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, in zl3073x_dpll_device_register()
2011 if (IS_ERR(zldpll->dpll_dev)) { in zl3073x_dpll_device_register()
2012 rc = PTR_ERR(zldpll->dpll_dev); in zl3073x_dpll_device_register()
2013 zldpll->dpll_dev = NULL; in zl3073x_dpll_device_register()
2018 rc = dpll_device_register(zldpll->dpll_dev, in zl3073x_dpll_device_register()
2019 zl3073x_prop_dpll_type_get(zldev, zldpll->id), in zl3073x_dpll_device_register()
2022 dpll_device_put(zldpll->dpll_dev); in zl3073x_dpll_device_register()
2023 zldpll->dpll_dev = NULL; in zl3073x_dpll_device_register()
2030 * zl3073x_dpll_device_unregister - unregister DPLL device
2033 * Unregisters given DPLL device from DPLL sub-system previously registered
2039 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); in zl3073x_dpll_device_unregister()
2041 cancel_work_sync(&zldpll->change_work); in zl3073x_dpll_device_unregister()
2043 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, in zl3073x_dpll_device_unregister()
2045 dpll_device_put(zldpll->dpll_dev); in zl3073x_dpll_device_unregister()
2046 zldpll->dpll_dev = NULL; in zl3073x_dpll_device_unregister()
2050 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change
2060 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_pin_phase_offset_check()
2061 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_pin_phase_offset_check()
2067 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_pin_phase_offset_check()
2076 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) { in zl3073x_dpll_pin_phase_offset_check()
2077 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); in zl3073x_dpll_pin_phase_offset_check()
2078 } else if (zldpll->phase_monitor) { in zl3073x_dpll_pin_phase_offset_check()
2085 dev_err(zldev->dev, in zl3073x_dpll_pin_phase_offset_check()
2087 pin->label, ERR_PTR(rc)); in zl3073x_dpll_pin_phase_offset_check()
2104 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", in zl3073x_dpll_pin_phase_offset_check()
2114 if (phase_offset != pin->phase_offset) { in zl3073x_dpll_pin_phase_offset_check()
2115 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", in zl3073x_dpll_pin_phase_offset_check()
2116 pin->label, pin->phase_offset, phase_offset); in zl3073x_dpll_pin_phase_offset_check()
2117 pin->phase_offset = phase_offset; in zl3073x_dpll_pin_phase_offset_check()
2126 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change
2136 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_pin_ffo_check()
2137 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_pin_ffo_check()
2143 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_pin_ffo_check()
2146 dev_err(zldev->dev, "Failed to read %s refmon status: %pe\n", in zl3073x_dpll_pin_ffo_check()
2147 pin->label, ERR_PTR(rc)); in zl3073x_dpll_pin_ffo_check()
2160 if (pin->freq_offset != ffo) { in zl3073x_dpll_pin_ffo_check()
2161 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n", in zl3073x_dpll_pin_ffo_check()
2162 pin->label, pin->freq_offset, ffo); in zl3073x_dpll_pin_ffo_check()
2163 pin->freq_offset = ffo; in zl3073x_dpll_pin_ffo_check()
2172 * zl3073x_dpll_changes_check - check for changes and send notifications
2183 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_changes_check()
2185 struct device *dev = zldev->dev; in zl3073x_dpll_changes_check()
2189 zldpll->check_count++; in zl3073x_dpll_changes_check()
2192 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, in zl3073x_dpll_changes_check()
2196 zldpll->id, ERR_PTR(rc)); in zl3073x_dpll_changes_check()
2201 if (zldpll->lock_status != lock_status) { in zl3073x_dpll_changes_check()
2202 zldpll->lock_status = lock_status; in zl3073x_dpll_changes_check()
2203 dpll_device_change_ntf(zldpll->dpll_dev); in zl3073x_dpll_changes_check()
2206 /* Input pin monitoring does make sense only in automatic in zl3073x_dpll_changes_check()
2209 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && in zl3073x_dpll_changes_check()
2210 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) in zl3073x_dpll_changes_check()
2216 if (zldpll->phase_monitor) { in zl3073x_dpll_changes_check()
2217 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); in zl3073x_dpll_changes_check()
2219 dev_err(zldev->dev, in zl3073x_dpll_changes_check()
2226 list_for_each_entry(pin, &zldpll->pins, list) { in zl3073x_dpll_changes_check()
2240 pin->label, zldpll->id, ERR_PTR(rc)); in zl3073x_dpll_changes_check()
2244 if (state != pin->pin_state) { in zl3073x_dpll_changes_check()
2245 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, in zl3073x_dpll_changes_check()
2246 pin->pin_state, state); in zl3073x_dpll_changes_check()
2247 pin->pin_state = state; in zl3073x_dpll_changes_check()
2252 if (zldpll->check_count % 2 == 0) { in zl3073x_dpll_changes_check()
2261 dpll_pin_change_ntf(pin->dpll_pin); in zl3073x_dpll_changes_check()
2266 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments
2298 * zl3073x_dpll_alloc - allocate DPLL device
2313 return ERR_PTR(-ENOMEM); in zl3073x_dpll_alloc()
2315 zldpll->dev = zldev; in zl3073x_dpll_alloc()
2316 zldpll->id = ch; in zl3073x_dpll_alloc()
2317 INIT_LIST_HEAD(&zldpll->pins); in zl3073x_dpll_alloc()
2318 INIT_WORK(&zldpll->change_work, zl3073x_dpll_change_work); in zl3073x_dpll_alloc()
2324 * zl3073x_dpll_free - free DPLL device
2332 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); in zl3073x_dpll_free()
2338 * zl3073x_dpll_register - register DPLL device and all its pins
2341 * Registers given DPLL device and all its pins into DPLL sub-system.
2364 * zl3073x_dpll_unregister - unregister DPLL device and its pins
2367 * Unregisters given DPLL device and all its pins from DPLL sub-system