Lines Matching +full:phase +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0-only
28 * struct zl3073x_dpll_pin - DPLL pin
39 * @phase_offset: last saved pin phase offset
65 * zl3073x_dpll_is_input_pin - check if the pin is input one
73 return pin->dir == DPLL_PIN_DIRECTION_INPUT; in zl3073x_dpll_is_input_pin()
77 * zl3073x_dpll_is_p_pin - check if the pin is P-pin
80 * Return: true if the pin is P-pin, false if it is N-pin
85 return zl3073x_is_p_pin(pin->id); in zl3073x_dpll_is_p_pin()
96 *direction = pin->dir; in zl3073x_dpll_pin_direction_get()
102 * zl3073x_dpll_input_ref_frequency_get - get input reference frequency
115 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_ref_frequency_get()
119 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_ref_frequency_get()
143 dev_err(zldev->dev, in zl3073x_dpll_input_ref_frequency_get()
146 return -EINVAL; in zl3073x_dpll_input_ref_frequency_get()
164 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_esync_get()
171 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_esync_get()
172 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, pin->id, &ref_freq); in zl3073x_dpll_input_pin_esync_get()
176 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_esync_get()
198 esync->freq = (esync_div == ZL_REF_ESYNC_DIV_1HZ) ? 1 : 0; in zl3073x_dpll_input_pin_esync_get()
199 esync->pulse = 25; in zl3073x_dpll_input_pin_esync_get()
202 esync->freq = 0; in zl3073x_dpll_input_pin_esync_get()
203 esync->pulse = 0; in zl3073x_dpll_input_pin_esync_get()
210 if (pin->esync_control && ref_freq > 1) { in zl3073x_dpll_input_pin_esync_get()
211 esync->range = esync_freq_ranges; in zl3073x_dpll_input_pin_esync_get()
212 esync->range_num = ARRAY_SIZE(esync_freq_ranges); in zl3073x_dpll_input_pin_esync_get()
214 esync->range = NULL; in zl3073x_dpll_input_pin_esync_get()
215 esync->range_num = 0; in zl3073x_dpll_input_pin_esync_get()
229 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_esync_set()
234 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_esync_set()
237 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_esync_set()
282 *ffo = pin->freq_offset; in zl3073x_dpll_input_pin_ffo_get()
301 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_frequency_get()
317 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_frequency_set()
328 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_frequency_set()
331 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_frequency_set()
355 * zl3073x_dpll_selected_ref_get - get currently selected reference
359 * Check for currently selected reference the DPLL should be locked to
367 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_selected_ref_get()
371 switch (zldpll->refsel_mode) { in zl3073x_dpll_selected_ref_get()
375 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), in zl3073x_dpll_selected_ref_get()
383 /* Return the reference only if the DPLL is locked to it */ in zl3073x_dpll_selected_ref_get()
391 *ref = zldpll->forced_ref; in zl3073x_dpll_selected_ref_get()
403 * zl3073x_dpll_selected_ref_set - select reference in manual mode
408 * locked to.
415 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_selected_ref_set()
419 mode = zldpll->refsel_mode; in zl3073x_dpll_selected_ref_set()
425 switch (zldpll->lock_status) { in zl3073x_dpll_selected_ref_set()
437 ref = zldpll->forced_ref; in zl3073x_dpll_selected_ref_set()
438 } else if (ref == zldpll->forced_ref) { in zl3073x_dpll_selected_ref_set()
439 /* No register update - same mode and same ref */ in zl3073x_dpll_selected_ref_set()
447 /* No register update - keep current mode */ in zl3073x_dpll_selected_ref_set()
457 return -EOPNOTSUPP; in zl3073x_dpll_selected_ref_set()
465 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), in zl3073x_dpll_selected_ref_set()
471 zldpll->refsel_mode = mode; in zl3073x_dpll_selected_ref_set()
472 zldpll->forced_ref = ref; in zl3073x_dpll_selected_ref_set()
478 * zl3073x_dpll_connected_ref_get - get currently connected reference
482 * Looks for currently connected the DPLL is locked to and stores its index
490 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_connected_ref_get()
523 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_phase_offset_get()
534 /* Report phase offset only for currently connected pin if the phase in zl3073x_dpll_input_pin_phase_offset_get()
537 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_phase_offset_get()
538 if (!zldpll->phase_monitor && ref != conn_ref) { in zl3073x_dpll_input_pin_phase_offset_get()
549 /* Report phase offset only if the input pin signal is present */ in zl3073x_dpll_input_pin_phase_offset_get()
556 ref_phase = pin->phase_offset; in zl3073x_dpll_input_pin_phase_offset_get()
558 /* The DPLL being locked to a higher freq than the current ref in zl3073x_dpll_input_pin_phase_offset_get()
559 * the phase offset is modded to the period of the signal in zl3073x_dpll_input_pin_phase_offset_get()
560 * the dpll is locked to. in zl3073x_dpll_input_pin_phase_offset_get()
582 ref_phase -= conn_period * div_factor; in zl3073x_dpll_input_pin_phase_offset_get()
600 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_phase_adjust_get()
606 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_phase_adjust_get()
609 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_phase_adjust_get()
615 /* Read current phase offset compensation */ in zl3073x_dpll_input_pin_phase_adjust_get()
626 *phase_adjust = (s32)-phase_comp; in zl3073x_dpll_input_pin_phase_adjust_get()
640 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_input_pin_phase_adjust_set()
649 phase_comp = -phase_adjust; in zl3073x_dpll_input_pin_phase_adjust_set()
651 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_input_pin_phase_adjust_set()
654 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_phase_adjust_set()
671 * zl3073x_dpll_ref_prio_get - get priority for given input pin
683 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_ref_prio_get()
684 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_ref_prio_get()
688 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_ref_prio_get()
692 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); in zl3073x_dpll_ref_prio_get()
696 /* Read reference priority - one value for P&N pins (4 bits/pin) */ in zl3073x_dpll_ref_prio_get()
697 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_ref_prio_get()
713 * zl3073x_dpll_ref_prio_set - set priority for given input pin
724 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_ref_prio_set()
725 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_ref_prio_set()
729 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_ref_prio_set()
733 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); in zl3073x_dpll_ref_prio_set()
737 /* Read reference priority - one value shared between P&N pins */ in zl3073x_dpll_ref_prio_set()
738 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_ref_prio_set()
759 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); in zl3073x_dpll_ref_prio_set()
763 * zl3073x_dpll_ref_state_get - get status for given input pin
776 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_ref_state_get()
777 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_ref_state_get()
781 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_ref_state_get()
797 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && in zl3073x_dpll_ref_state_get()
798 pin->selectable) { in zl3073x_dpll_ref_state_get()
846 switch (zldpll->refsel_mode) { in zl3073x_dpll_input_pin_state_on_dpll_set()
852 new_ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_input_pin_state_on_dpll_set()
859 return -EINVAL; in zl3073x_dpll_input_pin_state_on_dpll_set()
867 if (pin->selectable) in zl3073x_dpll_input_pin_state_on_dpll_set()
871 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); in zl3073x_dpll_input_pin_state_on_dpll_set()
876 pin->selectable = true; in zl3073x_dpll_input_pin_state_on_dpll_set()
878 if (!pin->selectable) in zl3073x_dpll_input_pin_state_on_dpll_set()
887 /* Mark pin as non-selectable */ in zl3073x_dpll_input_pin_state_on_dpll_set()
888 pin->selectable = false; in zl3073x_dpll_input_pin_state_on_dpll_set()
892 return -EINVAL; in zl3073x_dpll_input_pin_state_on_dpll_set()
900 rc = -EOPNOTSUPP; in zl3073x_dpll_input_pin_state_on_dpll_set()
914 *prio = pin->prio; in zl3073x_dpll_input_pin_prio_get()
928 return -EINVAL; in zl3073x_dpll_input_pin_prio_set()
931 if (pin->selectable) { in zl3073x_dpll_input_pin_prio_set()
938 pin->prio = prio; in zl3073x_dpll_input_pin_prio_set()
952 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_esync_get()
954 struct device *dev = zldev->dev; in zl3073x_dpll_output_pin_esync_get()
962 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_esync_get()
964 /* If N-division is enabled, esync is not supported. The register used in zl3073x_dpll_output_pin_esync_get()
965 * for N-division is also used for the esync divider so both cannot in zl3073x_dpll_output_pin_esync_get()
971 return -EOPNOTSUPP; in zl3073x_dpll_output_pin_esync_get()
976 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_esync_get()
998 return -EINVAL; in zl3073x_dpll_output_pin_esync_get()
1010 esync->freq = 0; in zl3073x_dpll_output_pin_esync_get()
1011 esync->pulse = 0; in zl3073x_dpll_output_pin_esync_get()
1025 return -EINVAL; in zl3073x_dpll_output_pin_esync_get()
1034 esync->freq = synth_freq / output_div / esync_period; in zl3073x_dpll_output_pin_esync_get()
1041 esync->pulse = (50 * esync_width) / output_div; in zl3073x_dpll_output_pin_esync_get()
1047 if (pin->esync_control && (synth_freq / output_div) > 1) { in zl3073x_dpll_output_pin_esync_get()
1048 esync->range = esync_freq_ranges; in zl3073x_dpll_output_pin_esync_get()
1049 esync->range_num = ARRAY_SIZE(esync_freq_ranges); in zl3073x_dpll_output_pin_esync_get()
1051 esync->range = NULL; in zl3073x_dpll_output_pin_esync_get()
1052 esync->range_num = 0; in zl3073x_dpll_output_pin_esync_get()
1067 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_esync_set()
1073 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_esync_set()
1075 /* If N-division is enabled, esync is not supported. The register used in zl3073x_dpll_output_pin_esync_set()
1076 * for N-division is also used for the esync divider so both cannot in zl3073x_dpll_output_pin_esync_set()
1082 return -EOPNOTSUPP; in zl3073x_dpll_output_pin_esync_set()
1087 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_esync_set()
1129 dev_err(zldev->dev, in zl3073x_dpll_output_pin_esync_set()
1131 return -EINVAL; in zl3073x_dpll_output_pin_esync_set()
1165 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_frequency_get()
1167 struct device *dev = zldev->dev; in zl3073x_dpll_output_pin_frequency_get()
1172 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_frequency_get()
1176 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_frequency_get()
1192 return -EINVAL; in zl3073x_dpll_output_pin_frequency_get()
1205 /* For P-pin the resulting frequency is computed as in zl3073x_dpll_output_pin_frequency_get()
1211 /* For N-pin we have to divide additionally by in zl3073x_dpll_output_pin_frequency_get()
1213 * register that is used as N-pin divisor for these in zl3073x_dpll_output_pin_frequency_get()
1223 /* Check N-pin divisor for zero */ in zl3073x_dpll_output_pin_frequency_get()
1226 "Zero N-pin divisor for output %u got from device\n", in zl3073x_dpll_output_pin_frequency_get()
1228 return -EINVAL; in zl3073x_dpll_output_pin_frequency_get()
1231 /* Compute final divisor for N-pin */ in zl3073x_dpll_output_pin_frequency_get()
1254 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_frequency_set()
1256 struct device *dev = zldev->dev; in zl3073x_dpll_output_pin_frequency_set()
1263 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_frequency_set()
1271 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_frequency_set()
1282 /* For non N-divided signal formats the frequency is computed in zl3073x_dpll_output_pin_frequency_set()
1300 /* For N-divided signal format get current divisor */ in zl3073x_dpll_output_pin_frequency_set()
1309 return -EINVAL; in zl3073x_dpll_output_pin_frequency_set()
1312 /* Get N-pin divisor (shares the same register with esync */ in zl3073x_dpll_output_pin_frequency_set()
1317 /* Check N-pin divisor for zero */ in zl3073x_dpll_output_pin_frequency_set()
1320 "Zero N-pin divisor for output %u got from device\n", in zl3073x_dpll_output_pin_frequency_set()
1322 return -EINVAL; in zl3073x_dpll_output_pin_frequency_set()
1325 /* Compute current output frequency for P-pin */ in zl3073x_dpll_output_pin_frequency_set()
1328 /* Compute current N-pin frequency */ in zl3073x_dpll_output_pin_frequency_set()
1332 /* We are going to change output frequency for P-pin but in zl3073x_dpll_output_pin_frequency_set()
1333 * if the requested frequency is less than current N-pin in zl3073x_dpll_output_pin_frequency_set()
1335 * to compute N-pin divisor to keep its frequency unchanged. in zl3073x_dpll_output_pin_frequency_set()
1338 return -EINVAL; in zl3073x_dpll_output_pin_frequency_set()
1350 /* Compute new divisor for N-pin */ in zl3073x_dpll_output_pin_frequency_set()
1353 /* We are going to change frequency of N-pin but if in zl3073x_dpll_output_pin_frequency_set()
1354 * the requested freq is greater or equal than freq of P-pin in zl3073x_dpll_output_pin_frequency_set()
1355 * in the output pair we cannot compute divisor for the N-pin. in zl3073x_dpll_output_pin_frequency_set()
1359 return -EINVAL; in zl3073x_dpll_output_pin_frequency_set()
1361 /* Compute new divisor for N-pin */ in zl3073x_dpll_output_pin_frequency_set()
1365 /* Update divisor for the N-pin */ in zl3073x_dpll_output_pin_frequency_set()
1389 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_phase_adjust_get()
1396 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_phase_adjust_get()
1402 dev_err(zldev->dev, "Got zero synth frequency for output %u\n", in zl3073x_dpll_output_pin_phase_adjust_get()
1404 return -EINVAL; in zl3073x_dpll_output_pin_phase_adjust_get()
1407 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_phase_adjust_get()
1415 /* Read current output phase compensation */ in zl3073x_dpll_output_pin_phase_adjust_get()
1424 *phase_adjust = -phase_comp; in zl3073x_dpll_output_pin_phase_adjust_get()
1438 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_output_pin_phase_adjust_set()
1446 out = zl3073x_output_pin_out_get(pin->id); in zl3073x_dpll_output_pin_phase_adjust_set()
1453 * the given phase adjustment a multiple of half synth clock. in zl3073x_dpll_output_pin_phase_adjust_set()
1459 "Phase adjustment value has to be multiple of %d", in zl3073x_dpll_output_pin_phase_adjust_set()
1461 return -EINVAL; in zl3073x_dpll_output_pin_phase_adjust_set()
1468 phase_adjust = -phase_adjust; in zl3073x_dpll_output_pin_phase_adjust_set()
1470 guard(mutex)(&zldev->multiop_lock); in zl3073x_dpll_output_pin_phase_adjust_set()
1509 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_lock_status_get()
1513 switch (zldpll->refsel_mode) { in zl3073x_dpll_lock_status_get()
1525 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), in zl3073x_dpll_lock_status_get()
1543 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", in zl3073x_dpll_lock_status_get()
1558 switch (zldpll->refsel_mode) { in zl3073x_dpll_mode_get()
1573 return -EINVAL; in zl3073x_dpll_mode_get()
1587 if (zldpll->phase_monitor) in zl3073x_dpll_phase_offset_monitor_get()
1603 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); in zl3073x_dpll_phase_offset_monitor_set()
1643 * zl3073x_dpll_pin_alloc - allocate DPLL pin
1661 return ERR_PTR(-ENOMEM); in zl3073x_dpll_pin_alloc()
1663 pin->dpll = zldpll; in zl3073x_dpll_pin_alloc()
1664 pin->dir = dir; in zl3073x_dpll_pin_alloc()
1665 pin->id = id; in zl3073x_dpll_pin_alloc()
1671 * zl3073x_dpll_pin_free - deallocate DPLL pin
1679 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); in zl3073x_dpll_pin_free()
1685 * zl3073x_dpll_pin_register - register DPLL pin
1689 * Registers given DPLL pin into DPLL sub-system.
1696 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_pin_register()
1702 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); in zl3073x_dpll_pin_register()
1707 strscpy(pin->label, props->package_label); in zl3073x_dpll_pin_register()
1708 pin->esync_control = props->esync_control; in zl3073x_dpll_pin_register()
1711 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); in zl3073x_dpll_pin_register()
1715 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { in zl3073x_dpll_pin_register()
1716 /* Clamp prio to max value & mark pin non-selectable */ in zl3073x_dpll_pin_register()
1717 pin->prio = ZL_DPLL_REF_PRIO_MAX; in zl3073x_dpll_pin_register()
1718 pin->selectable = false; in zl3073x_dpll_pin_register()
1721 pin->selectable = true; in zl3073x_dpll_pin_register()
1726 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, in zl3073x_dpll_pin_register()
1727 &props->dpll_props); in zl3073x_dpll_pin_register()
1728 if (IS_ERR(pin->dpll_pin)) { in zl3073x_dpll_pin_register()
1729 rc = PTR_ERR(pin->dpll_pin); in zl3073x_dpll_pin_register()
1739 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); in zl3073x_dpll_pin_register()
1749 dpll_pin_put(pin->dpll_pin); in zl3073x_dpll_pin_register()
1751 pin->dpll_pin = NULL; in zl3073x_dpll_pin_register()
1759 * zl3073x_dpll_pin_unregister - unregister DPLL pin
1767 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_pin_unregister()
1770 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); in zl3073x_dpll_pin_unregister()
1778 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); in zl3073x_dpll_pin_unregister()
1780 dpll_pin_put(pin->dpll_pin); in zl3073x_dpll_pin_unregister()
1781 pin->dpll_pin = NULL; in zl3073x_dpll_pin_unregister()
1785 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins
1796 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { in zl3073x_dpll_pins_unregister()
1798 list_del(&pin->list); in zl3073x_dpll_pins_unregister()
1804 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable
1811 * differential signal type only P-pin is reported as registrable.
1821 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_pin_is_registrable()
1831 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) in zl3073x_dpll_pin_is_registrable()
1843 if (zl3073x_out_dpll_get(zldev, out) != zldpll->id) { in zl3073x_dpll_pin_is_registrable()
1844 dev_dbg(zldev->dev, in zl3073x_dpll_pin_is_registrable()
1855 /* Skip N-pin if the corresponding input/output is differential */ in zl3073x_dpll_pin_is_registrable()
1857 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", in zl3073x_dpll_pin_is_registrable()
1865 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, in zl3073x_dpll_pin_is_registrable()
1875 * zl3073x_dpll_pins_register - register all registerable DPLL pins
1898 id = index - ZL3073X_NUM_INPUT_PINS; in zl3073x_dpll_pins_register()
1916 list_add(&pin->list, &zldpll->pins); in zl3073x_dpll_pins_register()
1928 * zl3073x_dpll_device_register - register DPLL device
1931 * Registers given DPLL device into DPLL sub-system.
1938 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_device_register()
1943 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), in zl3073x_dpll_device_register()
1949 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, in zl3073x_dpll_device_register()
1951 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, in zl3073x_dpll_device_register()
1954 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, in zl3073x_dpll_device_register()
1956 if (IS_ERR(zldpll->dpll_dev)) { in zl3073x_dpll_device_register()
1957 rc = PTR_ERR(zldpll->dpll_dev); in zl3073x_dpll_device_register()
1958 zldpll->dpll_dev = NULL; in zl3073x_dpll_device_register()
1963 rc = dpll_device_register(zldpll->dpll_dev, in zl3073x_dpll_device_register()
1964 zl3073x_prop_dpll_type_get(zldev, zldpll->id), in zl3073x_dpll_device_register()
1967 dpll_device_put(zldpll->dpll_dev); in zl3073x_dpll_device_register()
1968 zldpll->dpll_dev = NULL; in zl3073x_dpll_device_register()
1975 * zl3073x_dpll_device_unregister - unregister DPLL device
1978 * Unregisters given DPLL device from DPLL sub-system previously registered
1984 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); in zl3073x_dpll_device_unregister()
1986 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, in zl3073x_dpll_device_unregister()
1988 dpll_device_put(zldpll->dpll_dev); in zl3073x_dpll_device_unregister()
1989 zldpll->dpll_dev = NULL; in zl3073x_dpll_device_unregister()
1993 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change
1996 * Check for the change of DPLL to connected pin phase offset change.
1998 * Return: true on phase offset change, false otherwise
2003 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_pin_phase_offset_check()
2004 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_pin_phase_offset_check()
2010 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_pin_phase_offset_check()
2012 /* Select register to read phase offset value depending on pin and in zl3073x_dpll_pin_phase_offset_check()
2013 * phase monitor state: in zl3073x_dpll_pin_phase_offset_check()
2015 * 2) For other pins use appropriate ref_phase register if the phase in zl3073x_dpll_pin_phase_offset_check()
2019 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) { in zl3073x_dpll_pin_phase_offset_check()
2020 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); in zl3073x_dpll_pin_phase_offset_check()
2021 } else if (zldpll->phase_monitor) { in zl3073x_dpll_pin_phase_offset_check()
2028 dev_err(zldev->dev, in zl3073x_dpll_pin_phase_offset_check()
2030 pin->label, ERR_PTR(rc)); in zl3073x_dpll_pin_phase_offset_check()
2040 /* The pin is not connected or phase monitor disabled */ in zl3073x_dpll_pin_phase_offset_check()
2044 /* Read measured phase offset value */ in zl3073x_dpll_pin_phase_offset_check()
2047 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", in zl3073x_dpll_pin_phase_offset_check()
2057 if (phase_offset != pin->phase_offset) { in zl3073x_dpll_pin_phase_offset_check()
2058 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", in zl3073x_dpll_pin_phase_offset_check()
2059 pin->label, pin->phase_offset, phase_offset); in zl3073x_dpll_pin_phase_offset_check()
2060 pin->phase_offset = phase_offset; in zl3073x_dpll_pin_phase_offset_check()
2069 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change
2079 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_pin_ffo_check()
2080 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_pin_ffo_check()
2086 ref = zl3073x_input_pin_ref_get(pin->id); in zl3073x_dpll_pin_ffo_check()
2089 dev_err(zldev->dev, "Failed to read %s refmon status: %pe\n", in zl3073x_dpll_pin_ffo_check()
2090 pin->label, ERR_PTR(rc)); in zl3073x_dpll_pin_ffo_check()
2103 if (pin->freq_offset != ffo) { in zl3073x_dpll_pin_ffo_check()
2104 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n", in zl3073x_dpll_pin_ffo_check()
2105 pin->label, pin->freq_offset, ffo); in zl3073x_dpll_pin_ffo_check()
2106 pin->freq_offset = ffo; in zl3073x_dpll_pin_ffo_check()
2115 * zl3073x_dpll_changes_check - check for changes and send notifications
2126 struct zl3073x_dev *zldev = zldpll->dev; in zl3073x_dpll_changes_check()
2128 struct device *dev = zldev->dev; in zl3073x_dpll_changes_check()
2132 zldpll->check_count++; in zl3073x_dpll_changes_check()
2135 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, in zl3073x_dpll_changes_check()
2139 zldpll->id, ERR_PTR(rc)); in zl3073x_dpll_changes_check()
2144 if (zldpll->lock_status != lock_status) { in zl3073x_dpll_changes_check()
2145 zldpll->lock_status = lock_status; in zl3073x_dpll_changes_check()
2146 dpll_device_change_ntf(zldpll->dpll_dev); in zl3073x_dpll_changes_check()
2152 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && in zl3073x_dpll_changes_check()
2153 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) in zl3073x_dpll_changes_check()
2156 /* Update phase offset latch registers for this DPLL if the phase in zl3073x_dpll_changes_check()
2159 if (zldpll->phase_monitor) { in zl3073x_dpll_changes_check()
2160 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); in zl3073x_dpll_changes_check()
2162 dev_err(zldev->dev, in zl3073x_dpll_changes_check()
2163 "Failed to update phase offsets: %pe\n", in zl3073x_dpll_changes_check()
2169 list_for_each_entry(pin, &zldpll->pins, list) { in zl3073x_dpll_changes_check()
2183 pin->label, zldpll->id, ERR_PTR(rc)); in zl3073x_dpll_changes_check()
2187 if (state != pin->pin_state) { in zl3073x_dpll_changes_check()
2188 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, in zl3073x_dpll_changes_check()
2189 pin->pin_state, state); in zl3073x_dpll_changes_check()
2190 pin->pin_state = state; in zl3073x_dpll_changes_check()
2194 /* Check for phase offset and ffo change once per second */ in zl3073x_dpll_changes_check()
2195 if (zldpll->check_count % 2 == 0) { in zl3073x_dpll_changes_check()
2204 dpll_pin_change_ntf(pin->dpll_pin); in zl3073x_dpll_changes_check()
2209 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments
2212 * Performs initial fine phase adjustments needed per datasheet.
2241 * zl3073x_dpll_alloc - allocate DPLL device
2256 return ERR_PTR(-ENOMEM); in zl3073x_dpll_alloc()
2258 zldpll->dev = zldev; in zl3073x_dpll_alloc()
2259 zldpll->id = ch; in zl3073x_dpll_alloc()
2260 INIT_LIST_HEAD(&zldpll->pins); in zl3073x_dpll_alloc()
2266 * zl3073x_dpll_free - free DPLL device
2274 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); in zl3073x_dpll_free()
2280 * zl3073x_dpll_register - register DPLL device and all its pins
2283 * Registers given DPLL device and all its pins into DPLL sub-system.
2306 * zl3073x_dpll_unregister - unregister DPLL device and its pins
2309 * Unregisters given DPLL device and all its pins from DPLL sub-system