Lines Matching defs:dpll_priv
90 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_pin_direction_get()
159 void *dpll_priv, in zl3073x_dpll_input_pin_esync_get()
225 void *dpll_priv, u64 freq, in zl3073x_dpll_input_pin_esync_set()
277 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_input_pin_ffo_get()
291 void *dpll_priv, u64 *frequency, in zl3073x_dpll_input_pin_frequency_get()
313 void *dpll_priv, u64 frequency, in zl3073x_dpll_input_pin_frequency_set()
519 void *dpll_priv, s64 *phase_offset, in zl3073x_dpll_input_pin_phase_offset_get()
595 void *dpll_priv, in zl3073x_dpll_input_pin_phase_adjust_get()
635 void *dpll_priv, in zl3073x_dpll_input_pin_phase_adjust_set()
824 void *dpll_priv, in zl3073x_dpll_input_pin_state_on_dpll_get()
837 void *dpll_priv, in zl3073x_dpll_input_pin_state_on_dpll_set()
909 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_input_pin_prio_get()
921 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_input_pin_prio_set()
947 void *dpll_priv, in zl3073x_dpll_output_pin_esync_get()
1062 void *dpll_priv, u64 freq, in zl3073x_dpll_output_pin_esync_set()
1161 void *dpll_priv, u64 *frequency, in zl3073x_dpll_output_pin_frequency_get()
1250 void *dpll_priv, u64 frequency, in zl3073x_dpll_output_pin_frequency_set()
1384 void *dpll_priv, in zl3073x_dpll_output_pin_phase_adjust_get()
1433 void *dpll_priv, in zl3073x_dpll_output_pin_phase_adjust_set()
1492 void *dpll_priv, in zl3073x_dpll_output_pin_state_on_dpll_get()
1503 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_lock_status_get()
1553 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_mode_get()
1581 void *dpll_priv, u32 *factor, in zl3073x_dpll_phase_offset_avg_factor_get()
1602 void *dpll_priv, u32 factor, in zl3073x_dpll_phase_offset_avg_factor_set()
1634 void *dpll_priv, in zl3073x_dpll_phase_offset_monitor_get()
1650 void *dpll_priv, in zl3073x_dpll_phase_offset_monitor_set()