52  * dpll_msg_add_pin_handle - attach pin handle attribute to a given message
53  * @msg: pointer to sk_buff message to attach a pin handle
54  * @pin: pin pointer
58  * * -EMSGSIZE - no space in message to attach pin handle
60 static int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin)  in dpll_msg_add_pin_handle()  argument
62 	if (!pin)  in dpll_msg_add_pin_handle()
64 	if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id))  in dpll_msg_add_pin_handle()
75  * dpll_netdev_pin_handle_size - get size of pin handle attribute of a netdev
76  * @dev: netdev from which to get the pin
78  * Return: byte size of pin handle attribute, or 0 if @dev has no pin.
194 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_pin_prio()  argument
205 	ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,  in dpll_msg_add_pin_prio()
216 dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_pin_on_dpll_state()  argument
227 	ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_msg_add_pin_on_dpll_state()
238 dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_pin_direction()  argument
247 	ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,  in dpll_msg_add_pin_direction()
258 dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_pin_phase_adjust()  argument
269 	ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_msg_add_pin_phase_adjust()
281 dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_phase_offset()  argument
292 	ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_msg_add_phase_offset()
304 static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_ffo()  argument
315 	ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_msg_add_ffo()
326 dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_pin_freq()  argument
337 	ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,  in dpll_msg_add_pin_freq()
344 	for (fs = 0; fs < pin->prop.freq_supported_num; fs++) {  in dpll_msg_add_pin_freq()
348 		freq = pin->prop.freq_supported[fs].min;  in dpll_msg_add_pin_freq()
354 		freq = pin->prop.freq_supported[fs].max;  in dpll_msg_add_pin_freq()
367 dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_pin_esync()  argument
378 	ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,  in dpll_msg_add_pin_esync()
411 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq)  in dpll_pin_is_freq_supported()  argument
415 	for (fs = 0; fs < pin->prop.freq_supported_num; fs++)  in dpll_pin_is_freq_supported()
416 		if (freq >= pin->prop.freq_supported[fs].min &&  in dpll_pin_is_freq_supported()
417 		    freq <= pin->prop.freq_supported[fs].max)  in dpll_pin_is_freq_supported()
423 dpll_msg_add_pin_parents(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_pin_parents()  argument
434 	xa_for_each(&pin->parent_refs, index, ref) {  in dpll_msg_add_pin_parents()
438 		ppin = ref->pin;  in dpll_msg_add_pin_parents()
440 		ret = ops->state_on_pin_get(pin,  in dpll_msg_add_pin_parents()
441 					    dpll_pin_on_pin_priv(ppin, pin),  in dpll_msg_add_pin_parents()
466 dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_msg_add_pin_dplls()  argument
474 	xa_for_each(&pin->dpll_refs, index, ref) {  in dpll_msg_add_pin_dplls()
481 		ret = dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack);  in dpll_msg_add_pin_dplls()
484 		ret = dpll_msg_add_pin_prio(msg, pin, ref, extack);  in dpll_msg_add_pin_dplls()
487 		ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);  in dpll_msg_add_pin_dplls()
490 		ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);  in dpll_msg_add_pin_dplls()
504 dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,  in dpll_cmd_pin_get_one()  argument
507 	const struct dpll_pin_properties *prop = &pin->prop;  in dpll_cmd_pin_get_one()
511 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);  in dpll_cmd_pin_get_one()
514 	ret = dpll_msg_add_pin_handle(msg, pin);  in dpll_cmd_pin_get_one()
518 			   module_name(pin->module)))  in dpll_cmd_pin_get_one()
520 	if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id),  in dpll_cmd_pin_get_one()
521 			  &pin->clock_id, DPLL_A_PIN_PAD))  in dpll_cmd_pin_get_one()
537 	ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);  in dpll_cmd_pin_get_one()
546 	ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);  in dpll_cmd_pin_get_one()
549 	ret = dpll_msg_add_ffo(msg, pin, ref, extack);  in dpll_cmd_pin_get_one()
552 	ret = dpll_msg_add_pin_esync(msg, pin, ref, extack);  in dpll_cmd_pin_get_one()
555 	if (xa_empty(&pin->parent_refs))  in dpll_cmd_pin_get_one()
556 		ret = dpll_msg_add_pin_dplls(msg, pin, extack);  in dpll_cmd_pin_get_one()
558 		ret = dpll_msg_add_pin_parents(msg, pin, ref, extack);  in dpll_cmd_pin_get_one()
645 static bool dpll_pin_available(struct dpll_pin *pin)  in dpll_pin_available()  argument
650 	if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED))  in dpll_pin_available()
652 	xa_for_each(&pin->parent_refs, i, par_ref)  in dpll_pin_available()
653 		if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id,  in dpll_pin_available()
656 	xa_for_each(&pin->dpll_refs, i, par_ref)  in dpll_pin_available()
683 dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin)  in dpll_pin_event_send()  argument
689 	if (!dpll_pin_available(pin))  in dpll_pin_event_send()
699 	ret = dpll_cmd_pin_get_one(msg, pin, NULL);  in dpll_pin_event_send()
715 int dpll_pin_create_ntf(struct dpll_pin *pin)  in dpll_pin_create_ntf()  argument
717 	return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin);  in dpll_pin_create_ntf()
720 int dpll_pin_delete_ntf(struct dpll_pin *pin)  in dpll_pin_delete_ntf()  argument
722 	return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin);  in dpll_pin_delete_ntf()
725 static int __dpll_pin_change_ntf(struct dpll_pin *pin)  in __dpll_pin_change_ntf()  argument
727 	return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin);  in __dpll_pin_change_ntf()
731  * dpll_pin_change_ntf - notify that the pin has been changed
732  * @pin: registered pin pointer
737 int dpll_pin_change_ntf(struct dpll_pin *pin)  in dpll_pin_change_ntf()  argument
742 	ret = __dpll_pin_change_ntf(pin);  in dpll_pin_change_ntf()
750 dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a,  in dpll_pin_freq_set()  argument
760 	if (!dpll_pin_is_freq_supported(pin, freq)) {  in dpll_pin_freq_set()
765 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_freq_set()
772 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);  in dpll_pin_freq_set()
775 	ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,  in dpll_pin_freq_set()
784 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_freq_set()
787 		ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_pin_freq_set()
796 	__dpll_pin_change_ntf(pin);  in dpll_pin_freq_set()
801 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_freq_set()
806 		if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_pin_freq_set()
814 dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a,  in dpll_pin_esync_set()  argument
826 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_esync_set()
834 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);  in dpll_pin_esync_set()
837 	ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,  in dpll_pin_esync_set()
854 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_esync_set()
859 		pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin);  in dpll_pin_esync_set()
860 		ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll),  in dpll_pin_esync_set()
870 	__dpll_pin_change_ntf(pin);  in dpll_pin_esync_set()
875 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_esync_set()
882 		pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin);  in dpll_pin_esync_set()
883 		if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll),  in dpll_pin_esync_set()
891 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx,  in dpll_pin_on_pin_state_set()  argument
904 	      pin->prop.capabilities)) {  in dpll_pin_on_pin_state_set()
911 	parent_ref = xa_load(&pin->parent_refs, parent->pin_idx);  in dpll_pin_on_pin_state_set()
918 		pin_priv = dpll_pin_on_pin_priv(parent, pin);  in dpll_pin_on_pin_state_set()
920 		ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv,  in dpll_pin_on_pin_state_set()
925 	__dpll_pin_change_ntf(pin);  in dpll_pin_on_pin_state_set()
931 dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin,  in dpll_pin_state_set()  argument
940 	      pin->prop.capabilities)) {  in dpll_pin_state_set()
944 	ref = xa_load(&pin->dpll_refs, dpll->id);  in dpll_pin_state_set()
949 	ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_pin_state_set()
953 	__dpll_pin_change_ntf(pin);  in dpll_pin_state_set()
959 dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin,  in dpll_pin_prio_set()  argument
967 	      pin->prop.capabilities)) {  in dpll_pin_prio_set()
971 	ref = xa_load(&pin->dpll_refs, dpll->id);  in dpll_pin_prio_set()
976 	ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,  in dpll_pin_prio_set()
980 	__dpll_pin_change_ntf(pin);  in dpll_pin_prio_set()
986 dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll,  in dpll_pin_direction_set()  argument
995 	      pin->prop.capabilities)) {  in dpll_pin_direction_set()
999 	ref = xa_load(&pin->dpll_refs, dpll->id);  in dpll_pin_direction_set()
1004 	ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_pin_direction_set()
1008 	__dpll_pin_change_ntf(pin);  in dpll_pin_direction_set()
1014 dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,  in dpll_pin_phase_adj_set()  argument
1025 	if (phase_adj > pin->prop.phase_range.max ||  in dpll_pin_phase_adj_set()
1026 	    phase_adj < pin->prop.phase_range.min) {  in dpll_pin_phase_adj_set()
1032 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_phase_adj_set()
1039 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);  in dpll_pin_phase_adj_set()
1042 	ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_pin_phase_adj_set()
1052 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_phase_adj_set()
1055 		ret = ops->phase_adjust_set(pin,  in dpll_pin_phase_adj_set()
1056 					    dpll_pin_on_dpll_priv(dpll, pin),  in dpll_pin_phase_adj_set()
1067 	__dpll_pin_change_ntf(pin);  in dpll_pin_phase_adj_set()
1072 	xa_for_each(&pin->dpll_refs, i, ref) {  in dpll_pin_phase_adj_set()
1077 		if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin),  in dpll_pin_phase_adj_set()
1086 dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,  in dpll_pin_parent_device_set()  argument
1109 	ref = xa_load(&pin->dpll_refs, dpll->id);  in dpll_pin_parent_device_set()
1111 		NL_SET_ERR_MSG(extack, "pin not connected to given parent device");  in dpll_pin_parent_device_set()
1116 		ret = dpll_pin_state_set(dpll, pin, state, extack);  in dpll_pin_parent_device_set()
1122 		ret = dpll_pin_prio_set(dpll, pin, prio, extack);  in dpll_pin_parent_device_set()
1128 		ret = dpll_pin_direction_set(pin, dpll, direction, extack);  in dpll_pin_parent_device_set()
1136 dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest,  in dpll_pin_parent_pin_set()  argument
1154 		ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack);  in dpll_pin_parent_pin_set()
1163 dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info)  in dpll_pin_set_from_nlattr()  argument
1172 			ret = dpll_pin_freq_set(pin, a, info->extack);  in dpll_pin_set_from_nlattr()
1177 			ret = dpll_pin_phase_adj_set(pin, a, info->extack);  in dpll_pin_set_from_nlattr()
1182 			ret = dpll_pin_parent_device_set(pin, a, info->extack);  in dpll_pin_set_from_nlattr()
1187 			ret = dpll_pin_parent_pin_set(pin, a, info->extack);  in dpll_pin_set_from_nlattr()
1192 			ret = dpll_pin_esync_set(pin, a, info->extack);  in dpll_pin_set_from_nlattr()
1209 	struct dpll_pin *pin_match = NULL, *pin;  in dpll_pin_find()  local
1214 	xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) {  in dpll_pin_find()
1215 		prop = &pin->prop;  in dpll_pin_find()
1216 		cid_match = clock_id ? pin->clock_id == clock_id : true;  in dpll_pin_find()
1217 		mod_match = mod_name_attr && module_name(pin->module) ?  in dpll_pin_find()
1219 				    module_name(pin->module)) : true;  in dpll_pin_find()
1236 			pin_match = pin;  in dpll_pin_find()
1306 	struct dpll_pin *pin;  in dpll_nl_pin_id_get_doit()  local
1320 	pin = dpll_pin_find_from_nlattr(info);  in dpll_nl_pin_id_get_doit()
1321 	if (!IS_ERR(pin)) {  in dpll_nl_pin_id_get_doit()
1322 		if (!dpll_pin_available(pin)) {  in dpll_nl_pin_id_get_doit()
1326 		ret = dpll_msg_add_pin_handle(msg, pin);  in dpll_nl_pin_id_get_doit()
1339 	struct dpll_pin *pin = info->user_ptr[0];  in dpll_nl_pin_get_doit()  local
1344 	if (!pin)  in dpll_nl_pin_get_doit()
1355 	ret = dpll_cmd_pin_get_one(msg, pin, info->extack);  in dpll_nl_pin_get_doit()
1368 	struct dpll_pin *pin;  in dpll_nl_pin_get_dumpit()  local
1374 	xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED,  in dpll_nl_pin_get_dumpit()
1376 		if (!dpll_pin_available(pin))  in dpll_nl_pin_get_dumpit()
1386 		ret = dpll_cmd_pin_get_one(skb, pin, cb->extack);  in dpll_nl_pin_get_dumpit()
1404 	struct dpll_pin *pin = info->user_ptr[0];  in dpll_nl_pin_set_doit()  local
1406 	return dpll_pin_set_from_nlattr(pin, info);  in dpll_nl_pin_set_doit()
1633 		NL_SET_ERR_MSG(info->extack, "pin not found");  in dpll_pin_pre_doit()