Lines Matching refs:XILINX_DMA_REG_DMASR
81 #define XILINX_DMA_REG_DMASR 0x0004 macro
1314 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_dma_stop_transfer()
1329 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_cdma_stop_transfer()
1346 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_dma_start()
1352 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_start()
1764 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_reset()
1879 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); in xilinx_dma_irq_handler()
1883 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, in xilinx_dma_irq_handler()
1896 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, in xilinx_dma_irq_handler()
2496 XILINX_DMA_REG_DMASR)); in xilinx_dma_terminate_all()
2937 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & in xilinx_dma_chan_probe()