Lines Matching refs:tdc
184 int (*terminate)(struct tegra_dma_channel *tdc);
223 struct tegra_dma_channel *tdc; member
261 static inline void tdc_write(struct tegra_dma_channel *tdc, in tdc_write() argument
264 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_write()
267 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg) in tdc_read() argument
269 return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_read()
282 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) in tdc2dev() argument
284 return tdc->vc.chan.device->dev; in tdc2dev()
287 static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc) in tegra_dma_dump_chan_regs() argument
289 dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n", in tegra_dma_dump_chan_regs()
290 tdc->id, tdc->name); in tegra_dma_dump_chan_regs()
291 dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n", in tegra_dma_dump_chan_regs()
292 tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR), in tegra_dma_dump_chan_regs()
293 tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS), in tegra_dma_dump_chan_regs()
294 tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE), in tegra_dma_dump_chan_regs()
295 tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR), in tegra_dma_dump_chan_regs()
296 tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR) in tegra_dma_dump_chan_regs()
298 dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n", in tegra_dma_dump_chan_regs()
299 tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ), in tegra_dma_dump_chan_regs()
300 tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ), in tegra_dma_dump_chan_regs()
301 tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT), in tegra_dma_dump_chan_regs()
302 tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT), in tegra_dma_dump_chan_regs()
303 tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS) in tegra_dma_dump_chan_regs()
305 dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n", in tegra_dma_dump_chan_regs()
306 tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS)); in tegra_dma_dump_chan_regs()
309 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc, in tegra_dma_sid_reserve() argument
312 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_reserve()
313 int sid = tdc->slave_id; in tegra_dma_sid_reserve()
335 tdc->sid_dir = direction; in tegra_dma_sid_reserve()
340 static void tegra_dma_sid_free(struct tegra_dma_channel *tdc) in tegra_dma_sid_free() argument
342 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_free()
343 int sid = tdc->slave_id; in tegra_dma_sid_free()
345 switch (tdc->sid_dir) { in tegra_dma_sid_free()
356 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_sid_free()
367 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_slave_config() local
369 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
370 tdc->config_init = true; in tegra_dma_slave_config()
375 static int tegra_dma_pause(struct tegra_dma_channel *tdc) in tegra_dma_pause() argument
380 val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); in tegra_dma_pause()
382 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); in tegra_dma_pause()
385 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_pause()
386 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_pause()
393 dev_err(tdc2dev(tdc), "DMA pause timed out\n"); in tegra_dma_pause()
394 tegra_dma_dump_chan_regs(tdc); in tegra_dma_pause()
397 tdc->status = DMA_PAUSED; in tegra_dma_pause()
404 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_device_pause() local
408 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_pause()
411 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_pause()
412 ret = tegra_dma_pause(tdc); in tegra_dma_device_pause()
413 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_pause()
418 static void tegra_dma_resume(struct tegra_dma_channel *tdc) in tegra_dma_resume() argument
422 val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); in tegra_dma_resume()
424 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); in tegra_dma_resume()
426 tdc->status = DMA_IN_PROGRESS; in tegra_dma_resume()
431 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_device_resume() local
434 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_resume()
437 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_resume()
438 tegra_dma_resume(tdc); in tegra_dma_device_resume()
439 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_resume()
444 static inline int tegra_dma_pause_noerr(struct tegra_dma_channel *tdc) in tegra_dma_pause_noerr() argument
451 tegra_dma_pause(tdc); in tegra_dma_pause_noerr()
455 static void tegra_dma_disable(struct tegra_dma_channel *tdc) in tegra_dma_disable() argument
459 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); in tegra_dma_disable()
466 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); in tegra_dma_disable()
469 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); in tegra_dma_disable()
471 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); in tegra_dma_disable()
472 tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status); in tegra_dma_disable()
476 static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc) in tegra_dma_configure_next_sg() argument
478 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_configure_next_sg()
490 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_configure_next_sg()
491 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_configure_next_sg()
500 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_configure_next_sg()
501 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_configure_next_sg()
502 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_configure_next_sg()
503 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_configure_next_sg()
506 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, in tegra_dma_configure_next_sg()
510 static void tegra_dma_start(struct tegra_dma_channel *tdc) in tegra_dma_start() argument
512 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_start()
517 vdesc = vchan_next_desc(&tdc->vc); in tegra_dma_start()
523 dma_desc->tdc = tdc; in tegra_dma_start()
524 tdc->dma_desc = dma_desc; in tegra_dma_start()
526 tegra_dma_resume(tdc); in tegra_dma_start()
531 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
532 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0); in tegra_dma_start()
533 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_start()
534 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_start()
535 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_start()
536 tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); in tegra_dma_start()
537 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); in tegra_dma_start()
538 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); in tegra_dma_start()
539 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
542 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, in tegra_dma_start()
546 static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc) in tegra_dma_xfer_complete() argument
548 vchan_cookie_complete(&tdc->dma_desc->vd); in tegra_dma_xfer_complete()
550 tegra_dma_sid_free(tdc); in tegra_dma_xfer_complete()
551 tdc->dma_desc = NULL; in tegra_dma_xfer_complete()
552 tdc->status = DMA_COMPLETE; in tegra_dma_xfer_complete()
555 static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc, in tegra_dma_chan_decode_error() argument
560 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
561 "GPCDMA CH%d bm fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
565 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
566 "GPCDMA CH%d peripheral fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
570 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
571 "GPCDMA CH%d illegal peripheral id\n", tdc->id); in tegra_dma_chan_decode_error()
575 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
576 "GPCDMA CH%d illegal stream id\n", tdc->id); in tegra_dma_chan_decode_error()
580 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
581 "GPCDMA CH%d mc slave error\n", tdc->id); in tegra_dma_chan_decode_error()
585 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
586 "GPCDMA CH%d mmio slave error\n", tdc->id); in tegra_dma_chan_decode_error()
590 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
591 "GPCDMA CH%d security violation %x\n", tdc->id, in tegra_dma_chan_decode_error()
598 struct tegra_dma_channel *tdc = dev_id; in tegra_dma_isr() local
599 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_isr()
604 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS); in tegra_dma_isr()
606 tegra_dma_chan_decode_error(tdc, status); in tegra_dma_isr()
607 tegra_dma_dump_chan_regs(tdc); in tegra_dma_isr()
608 tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF); in tegra_dma_isr()
611 spin_lock(&tdc->vc.lock); in tegra_dma_isr()
612 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); in tegra_dma_isr()
616 tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_isr()
627 tegra_dma_configure_next_sg(tdc); in tegra_dma_isr()
631 tegra_dma_xfer_complete(tdc); in tegra_dma_isr()
633 tegra_dma_start(tdc); in tegra_dma_isr()
637 spin_unlock(&tdc->vc.lock); in tegra_dma_isr()
643 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_issue_pending() local
646 if (tdc->dma_desc) in tegra_dma_issue_pending()
649 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
650 if (vchan_issue_pending(&tdc->vc)) in tegra_dma_issue_pending()
651 tegra_dma_start(tdc); in tegra_dma_issue_pending()
660 if (tdc->dma_desc && tdc->dma_desc->cyclic) in tegra_dma_issue_pending()
661 tegra_dma_configure_next_sg(tdc); in tegra_dma_issue_pending()
663 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
666 static int tegra_dma_stop_client(struct tegra_dma_channel *tdc) in tegra_dma_stop_client() argument
676 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); in tegra_dma_stop_client()
679 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); in tegra_dma_stop_client()
688 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_stop_client()
689 tdc->chan_base_offset + in tegra_dma_stop_client()
697 dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n"); in tegra_dma_stop_client()
698 tegra_dma_dump_chan_regs(tdc); in tegra_dma_stop_client()
706 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_terminate_all() local
711 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
713 if (tdc->dma_desc) { in tegra_dma_terminate_all()
714 err = tdc->tdma->chip_data->terminate(tdc); in tegra_dma_terminate_all()
716 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
720 vchan_terminate_vdesc(&tdc->dma_desc->vd); in tegra_dma_terminate_all()
721 tegra_dma_disable(tdc); in tegra_dma_terminate_all()
722 tdc->dma_desc = NULL; in tegra_dma_terminate_all()
725 tdc->status = DMA_COMPLETE; in tegra_dma_terminate_all()
726 tegra_dma_sid_free(tdc); in tegra_dma_terminate_all()
727 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_dma_terminate_all()
728 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
730 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_dma_terminate_all()
735 static int tegra_dma_get_residual(struct tegra_dma_channel *tdc) in tegra_dma_get_residual() argument
737 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_get_residual()
742 wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT); in tegra_dma_get_residual()
749 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); in tegra_dma_get_residual()
768 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_tx_status() local
779 if (tdc->status == DMA_PAUSED) in tegra_dma_tx_status()
782 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_tx_status()
783 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_dma_tx_status()
788 } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) { in tegra_dma_tx_status()
789 residual = tegra_dma_get_residual(tdc); in tegra_dma_tx_status()
792 dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie); in tegra_dma_tx_status()
794 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_tx_status()
799 static inline int get_bus_width(struct tegra_dma_channel *tdc, in get_bus_width() argument
810 dev_err(tdc2dev(tdc), "given slave bus width is not supported\n"); in get_bus_width()
815 static unsigned int get_burst_size(struct tegra_dma_channel *tdc, in get_burst_size() argument
838 static int get_transfer_param(struct tegra_dma_channel *tdc, in get_transfer_param() argument
848 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
849 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
850 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
851 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
855 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
856 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
857 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
858 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
862 dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); in get_transfer_param()
872 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_memset() local
873 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memset()
879 dev_err(tdc2dev(tdc), in tegra_dma_prep_dma_memset()
896 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); in tegra_dma_prep_dma_memset()
932 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memset()
939 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_memcpy() local
945 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memcpy()
947 dev_err(tdc2dev(tdc), in tegra_dma_prep_dma_memcpy()
964 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); in tegra_dma_prep_dma_memcpy()
1002 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memcpy()
1010 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_slave_sg() local
1011 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_slave_sg()
1021 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
1022 dev_err(tdc2dev(tdc), "DMA channel is not configured\n"); in tegra_dma_prep_slave_sg()
1026 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len); in tegra_dma_prep_slave_sg()
1030 ret = tegra_dma_sid_reserve(tdc, direction); in tegra_dma_prep_slave_sg()
1034 ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr, in tegra_dma_prep_slave_sg()
1042 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_slave_sg()
1052 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); in tegra_dma_prep_slave_sg()
1089 dev_err(tdc2dev(tdc), in tegra_dma_prep_slave_sg()
1095 mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len); in tegra_dma_prep_slave_sg()
1122 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_slave_sg()
1133 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_cyclic() local
1140 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n"); in tegra_dma_prep_dma_cyclic()
1144 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1145 dev_err(tdc2dev(tdc), "DMA slave is not configured\n"); in tegra_dma_prep_dma_cyclic()
1149 ret = tegra_dma_sid_reserve(tdc, direction); in tegra_dma_prep_dma_cyclic()
1158 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n"); in tegra_dma_prep_dma_cyclic()
1163 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_cyclic()
1165 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n"); in tegra_dma_prep_dma_cyclic()
1169 ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr, in tegra_dma_prep_dma_cyclic()
1177 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_dma_cyclic()
1189 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); in tegra_dma_prep_dma_cyclic()
1219 mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len); in tegra_dma_prep_dma_cyclic()
1246 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_cyclic()
1251 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_alloc_chan_resources() local
1254 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc); in tegra_dma_alloc_chan_resources()
1256 dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name); in tegra_dma_alloc_chan_resources()
1260 dma_cookie_init(&tdc->vc.chan); in tegra_dma_alloc_chan_resources()
1261 tdc->config_init = false; in tegra_dma_alloc_chan_resources()
1267 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_chan_synchronize() local
1269 synchronize_irq(tdc->irq); in tegra_dma_chan_synchronize()
1270 vchan_synchronize(&tdc->vc); in tegra_dma_chan_synchronize()
1275 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_free_chan_resources() local
1277 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1280 synchronize_irq(tdc->irq); in tegra_dma_free_chan_resources()
1282 tasklet_kill(&tdc->vc.task); in tegra_dma_free_chan_resources()
1283 tdc->config_init = false; in tegra_dma_free_chan_resources()
1284 tdc->slave_id = -1; in tegra_dma_free_chan_resources()
1285 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_free_chan_resources()
1286 free_irq(tdc->irq, tdc); in tegra_dma_free_chan_resources()
1288 vchan_free_chan_resources(&tdc->vc); in tegra_dma_free_chan_resources()
1295 struct tegra_dma_channel *tdc; in tegra_dma_of_xlate() local
1302 tdc = to_tegra_dma_chan(chan); in tegra_dma_of_xlate()
1303 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1347 static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id) in tegra_dma_program_sid() argument
1349 unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); in tegra_dma_program_sid()
1357 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val); in tegra_dma_program_sid()
1410 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe() local
1416 tdc->irq = platform_get_irq(pdev, i); in tegra_dma_probe()
1417 if (tdc->irq < 0) in tegra_dma_probe()
1418 return tdc->irq; in tegra_dma_probe()
1420 tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET + in tegra_dma_probe()
1422 snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); in tegra_dma_probe()
1423 tdc->tdma = tdma; in tegra_dma_probe()
1424 tdc->id = i; in tegra_dma_probe()
1425 tdc->slave_id = -1; in tegra_dma_probe()
1427 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_dma_probe()
1428 tdc->vc.desc_free = tegra_dma_desc_free; in tegra_dma_probe()
1431 tegra_dma_program_sid(tdc, stream_id); in tegra_dma_probe()
1432 tdc->stream_id = stream_id; in tegra_dma_probe()
1501 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_suspend() local
1506 if (tdc->dma_desc) { in tegra_dma_pm_suspend()
1523 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_resume() local
1528 tegra_dma_program_sid(tdc, tdc->stream_id); in tegra_dma_pm_resume()