Lines Matching +full:tegra186 +full:- +full:mc
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/dma-mapping.h>
21 #include <dt-bindings/memory/tegra186-mc.h>
22 #include "virt-dma.h"
87 /* MC sequence register */
118 (GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT)
158 * on-flight burst and update DMA status register.
203 * sub-transfer as per requester details and hw support. This sub transfer
263 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_write()
268 return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_read()
283 return tdc->vc.chan.device->dev; in tdc2dev()
289 tdc->id, tdc->name); in tegra_dma_dump_chan_regs()
311 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_reserve()
312 int sid = tdc->slave_id; in tegra_dma_sid_reserve()
319 if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) { in tegra_dma_sid_reserve()
320 dev_err(tdma->dev, "slave id already in use\n"); in tegra_dma_sid_reserve()
321 return -EINVAL; in tegra_dma_sid_reserve()
325 if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) { in tegra_dma_sid_reserve()
326 dev_err(tdma->dev, "slave id already in use\n"); in tegra_dma_sid_reserve()
327 return -EINVAL; in tegra_dma_sid_reserve()
334 tdc->sid_dir = direction; in tegra_dma_sid_reserve()
341 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_free()
342 int sid = tdc->slave_id; in tegra_dma_sid_free()
344 switch (tdc->sid_dir) { in tegra_dma_sid_free()
346 clear_bit(sid, &tdma->sid_m2d_reserved); in tegra_dma_sid_free()
349 clear_bit(sid, &tdma->sid_d2m_reserved); in tegra_dma_sid_free()
355 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_sid_free()
368 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
369 tdc->config_init = true; in tegra_dma_slave_config()
383 /* Wait until busy bit is de-asserted */ in tegra_dma_pause()
384 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_pause()
385 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_pause()
405 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_pause()
406 return -ENOSYS; in tegra_dma_device_pause()
408 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_pause()
410 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_pause()
429 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_resume()
430 return -ENOSYS; in tegra_dma_device_resume()
432 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_resume()
434 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_resume()
473 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_configure_next_sg()
478 dma_desc->sg_idx++; in tegra_dma_configure_next_sg()
481 if (dma_desc->sg_idx == dma_desc->sg_count) in tegra_dma_configure_next_sg()
482 dma_desc->sg_idx = 0; in tegra_dma_configure_next_sg()
485 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_configure_next_sg()
486 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_configure_next_sg()
493 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; in tegra_dma_configure_next_sg()
495 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_configure_next_sg()
496 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_configure_next_sg()
497 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_configure_next_sg()
498 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_configure_next_sg()
502 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_configure_next_sg()
507 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_start()
512 vdesc = vchan_next_desc(&tdc->vc); in tegra_dma_start()
517 list_del(&vdesc->node); in tegra_dma_start()
518 dma_desc->tdc = tdc; in tegra_dma_start()
519 tdc->dma_desc = dma_desc; in tegra_dma_start()
524 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; in tegra_dma_start()
526 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
528 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_start()
529 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_start()
530 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_start()
531 tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); in tegra_dma_start()
532 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); in tegra_dma_start()
533 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); in tegra_dma_start()
534 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
538 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_start()
543 vchan_cookie_complete(&tdc->dma_desc->vd); in tegra_dma_xfer_complete()
546 tdc->dma_desc = NULL; in tegra_dma_xfer_complete()
554 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
555 "GPCDMA CH%d bm fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
559 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
560 "GPCDMA CH%d peripheral fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
564 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
565 "GPCDMA CH%d illegal peripheral id\n", tdc->id); in tegra_dma_chan_decode_error()
569 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
570 "GPCDMA CH%d illegal stream id\n", tdc->id); in tegra_dma_chan_decode_error()
574 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
575 "GPCDMA CH%d mc slave error\n", tdc->id); in tegra_dma_chan_decode_error()
579 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
580 "GPCDMA CH%d mmio slave error\n", tdc->id); in tegra_dma_chan_decode_error()
584 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
585 "GPCDMA CH%d security violation %x\n", tdc->id, in tegra_dma_chan_decode_error()
593 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_isr()
605 spin_lock(&tdc->vc.lock); in tegra_dma_isr()
616 sg_req = dma_desc->sg_req; in tegra_dma_isr()
617 dma_desc->bytes_xfer += sg_req[dma_desc->sg_idx].len; in tegra_dma_isr()
619 if (dma_desc->cyclic) { in tegra_dma_isr()
620 vchan_cyclic_callback(&dma_desc->vd); in tegra_dma_isr()
623 dma_desc->sg_idx++; in tegra_dma_isr()
624 if (dma_desc->sg_idx == dma_desc->sg_count) in tegra_dma_isr()
631 spin_unlock(&tdc->vc.lock); in tegra_dma_isr()
640 if (tdc->dma_desc) in tegra_dma_issue_pending()
643 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
644 if (vchan_issue_pending(&tdc->vc)) in tegra_dma_issue_pending()
654 if (tdc->dma_desc && tdc->dma_desc->cyclic) in tegra_dma_issue_pending()
657 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
682 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_stop_client()
683 tdc->chan_base_offset + in tegra_dma_stop_client()
705 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
707 if (tdc->dma_desc) { in tegra_dma_terminate_all()
708 err = tdc->tdma->chip_data->terminate(tdc); in tegra_dma_terminate_all()
710 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
714 vchan_terminate_vdesc(&tdc->dma_desc->vd); in tegra_dma_terminate_all()
716 tdc->dma_desc = NULL; in tegra_dma_terminate_all()
720 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_dma_terminate_all()
721 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
723 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_dma_terminate_all()
730 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_get_residual()
731 struct tegra_dma_sg_req *sg_req = dma_desc->sg_req; in tegra_dma_get_residual()
746 bytes_xfer = dma_desc->bytes_xfer + in tegra_dma_get_residual()
747 sg_req[dma_desc->sg_idx].len - (wcount * 4); in tegra_dma_get_residual()
749 if (dma_desc->bytes_req == bytes_xfer) in tegra_dma_get_residual()
752 residual = dma_desc->bytes_req - (bytes_xfer % dma_desc->bytes_req); in tegra_dma_get_residual()
772 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_tx_status()
773 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_dma_tx_status()
776 residual = dma_desc->bytes_req; in tegra_dma_tx_status()
778 } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) { in tegra_dma_tx_status()
784 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_tx_status()
801 return -EINVAL; in get_bus_width()
838 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
839 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
840 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
841 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
845 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
846 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
847 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
848 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
855 return -EINVAL; in get_transfer_param()
863 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memset()
887 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_memset()
896 /* Program outstanding MC requests */ in tegra_dma_prep_dma_memset()
905 dma_desc->bytes_req = len; in tegra_dma_prep_dma_memset()
906 dma_desc->sg_count = 1; in tegra_dma_prep_dma_memset()
907 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_memset()
915 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_memset()
921 dma_desc->cyclic = false; in tegra_dma_prep_dma_memset()
922 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memset()
935 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memcpy()
955 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_memcpy()
965 /* Program outstanding MC requests */ in tegra_dma_prep_dma_memcpy()
974 dma_desc->bytes_req = len; in tegra_dma_prep_dma_memcpy()
975 dma_desc->sg_count = 1; in tegra_dma_prep_dma_memcpy()
976 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_memcpy()
985 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_memcpy()
991 dma_desc->cyclic = false; in tegra_dma_prep_dma_memcpy()
992 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memcpy()
1001 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_slave_sg()
1011 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
1032 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_slave_sg()
1043 /* retain stream-id and clean rest */ in tegra_dma_prep_slave_sg()
1046 /* Set the address wrapping on both MC and MMIO side */ in tegra_dma_prep_slave_sg()
1054 /* Program 2 MC outstanding requests by default. */ in tegra_dma_prep_slave_sg()
1057 /* Setting MC burst size depending on MMIO burst size */ in tegra_dma_prep_slave_sg()
1067 dma_desc->sg_count = sg_len; in tegra_dma_prep_slave_sg()
1068 sg_req = dma_desc->sg_req; in tegra_dma_prep_slave_sg()
1086 dma_desc->bytes_req += len; in tegra_dma_prep_slave_sg()
1104 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_slave_sg()
1111 dma_desc->cyclic = false; in tegra_dma_prep_slave_sg()
1112 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_slave_sg()
1134 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1153 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_cyclic()
1167 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_dma_cyclic()
1180 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_cyclic()
1183 /* Set the address wrapping on both MC and MMIO side */ in tegra_dma_prep_dma_cyclic()
1189 /* Program 2 MC outstanding requests by default. */ in tegra_dma_prep_dma_cyclic()
1191 /* Setting MC burst size depending on MMIO burst size */ in tegra_dma_prep_dma_cyclic()
1203 dma_desc->bytes_req = buf_len; in tegra_dma_prep_dma_cyclic()
1204 dma_desc->sg_count = period_count; in tegra_dma_prep_dma_cyclic()
1205 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_cyclic()
1225 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_cyclic()
1234 dma_desc->cyclic = true; in tegra_dma_prep_dma_cyclic()
1236 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_cyclic()
1244 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc); in tegra_dma_alloc_chan_resources()
1246 dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name); in tegra_dma_alloc_chan_resources()
1250 dma_cookie_init(&tdc->vc.chan); in tegra_dma_alloc_chan_resources()
1251 tdc->config_init = false; in tegra_dma_alloc_chan_resources()
1259 synchronize_irq(tdc->irq); in tegra_dma_chan_synchronize()
1260 vchan_synchronize(&tdc->vc); in tegra_dma_chan_synchronize()
1267 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1270 synchronize_irq(tdc->irq); in tegra_dma_free_chan_resources()
1272 tasklet_kill(&tdc->vc.task); in tegra_dma_free_chan_resources()
1273 tdc->config_init = false; in tegra_dma_free_chan_resources()
1274 tdc->slave_id = -1; in tegra_dma_free_chan_resources()
1275 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_free_chan_resources()
1276 free_irq(tdc->irq, tdc); in tegra_dma_free_chan_resources()
1278 vchan_free_chan_resources(&tdc->vc); in tegra_dma_free_chan_resources()
1284 struct tegra_dma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
1288 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
1293 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1324 .compatible = "nvidia,tegra186-gpcdma",
1327 .compatible = "nvidia,tegra194-gpcdma",
1330 .compatible = "nvidia,tegra234-gpcdma",
1359 cdata = of_device_get_match_data(&pdev->dev); in tegra_dma_probe()
1361 tdma = devm_kzalloc(&pdev->dev, in tegra_dma_probe()
1362 struct_size(tdma, channels, cdata->nr_channels), in tegra_dma_probe()
1365 return -ENOMEM; in tegra_dma_probe()
1367 tdma->dev = &pdev->dev; in tegra_dma_probe()
1368 tdma->chip_data = cdata; in tegra_dma_probe()
1371 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); in tegra_dma_probe()
1372 if (IS_ERR(tdma->base_addr)) in tegra_dma_probe()
1373 return PTR_ERR(tdma->base_addr); in tegra_dma_probe()
1375 tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma"); in tegra_dma_probe()
1376 if (IS_ERR(tdma->rst)) { in tegra_dma_probe()
1377 return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst), in tegra_dma_probe()
1380 reset_control_reset(tdma->rst); in tegra_dma_probe()
1382 tdma->dma_dev.dev = &pdev->dev; in tegra_dma_probe()
1384 if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { in tegra_dma_probe()
1385 dev_err(&pdev->dev, "Missing iommu stream-id\n"); in tegra_dma_probe()
1386 return -EINVAL; in tegra_dma_probe()
1389 ret = device_property_read_u32(&pdev->dev, "dma-channel-mask", in tegra_dma_probe()
1390 &tdma->chan_mask); in tegra_dma_probe()
1392 dev_warn(&pdev->dev, in tegra_dma_probe()
1393 "Missing dma-channel-mask property, using default channel mask %#x\n", in tegra_dma_probe()
1395 tdma->chan_mask = TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK; in tegra_dma_probe()
1398 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_dma_probe()
1399 for (i = 0; i < cdata->nr_channels; i++) { in tegra_dma_probe()
1400 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe()
1403 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_probe()
1406 tdc->irq = platform_get_irq(pdev, i); in tegra_dma_probe()
1407 if (tdc->irq < 0) in tegra_dma_probe()
1408 return tdc->irq; in tegra_dma_probe()
1410 tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET + in tegra_dma_probe()
1411 i * cdata->channel_reg_size; in tegra_dma_probe()
1412 snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); in tegra_dma_probe()
1413 tdc->tdma = tdma; in tegra_dma_probe()
1414 tdc->id = i; in tegra_dma_probe()
1415 tdc->slave_id = -1; in tegra_dma_probe()
1417 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_dma_probe()
1418 tdc->vc.desc_free = tegra_dma_desc_free; in tegra_dma_probe()
1420 /* program stream-id for this channel */ in tegra_dma_probe()
1422 tdc->stream_id = stream_id; in tegra_dma_probe()
1425 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1426 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1427 dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1428 dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1429 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1435 tdma->dma_dev.copy_align = 2; in tegra_dma_probe()
1436 tdma->dma_dev.fill_align = 2; in tegra_dma_probe()
1437 tdma->dma_dev.device_alloc_chan_resources = in tegra_dma_probe()
1439 tdma->dma_dev.device_free_chan_resources = in tegra_dma_probe()
1441 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg; in tegra_dma_probe()
1442 tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy; in tegra_dma_probe()
1443 tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset; in tegra_dma_probe()
1444 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; in tegra_dma_probe()
1445 tdma->dma_dev.device_config = tegra_dma_slave_config; in tegra_dma_probe()
1446 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all; in tegra_dma_probe()
1447 tdma->dma_dev.device_tx_status = tegra_dma_tx_status; in tegra_dma_probe()
1448 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; in tegra_dma_probe()
1449 tdma->dma_dev.device_pause = tegra_dma_device_pause; in tegra_dma_probe()
1450 tdma->dma_dev.device_resume = tegra_dma_device_resume; in tegra_dma_probe()
1451 tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize; in tegra_dma_probe()
1452 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in tegra_dma_probe()
1454 ret = dma_async_device_register(&tdma->dma_dev); in tegra_dma_probe()
1456 dev_err_probe(&pdev->dev, ret, in tegra_dma_probe()
1461 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_dma_probe()
1464 dev_err_probe(&pdev->dev, ret, in tegra_dma_probe()
1467 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_probe()
1471 dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n", in tegra_dma_probe()
1472 hweight_long(tdma->chan_mask)); in tegra_dma_probe()
1481 of_dma_controller_free(pdev->dev.of_node); in tegra_dma_remove()
1482 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_remove()
1490 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_suspend()
1491 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_suspend()
1493 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_pm_suspend()
1496 if (tdc->dma_desc) { in tegra_dma_pm_suspend()
1497 dev_err(tdma->dev, "channel %u busy\n", i); in tegra_dma_pm_suspend()
1498 return -EBUSY; in tegra_dma_pm_suspend()
1510 reset_control_reset(tdma->rst); in tegra_dma_pm_resume()
1512 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_resume()
1513 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_resume()
1515 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_pm_resume()
1518 tegra_dma_program_sid(tdc, tdc->stream_id); in tegra_dma_pm_resume()
1530 .name = "tegra-gpcdma",