Lines Matching refs:STM32_DMA3_CCR
37 #define STM32_DMA3_CCR(x) (0x64 + 0x80 * (x)) macro
342 offset = STM32_DMA3_CCR(id); in stm32_dma3_chan_dump_reg()
755 writel_relaxed(chan->swdesc->ccr, ddata->base + STM32_DMA3_CCR(id)); in stm32_dma3_chan_start()
770 ccr = readl_relaxed(ddata->base + STM32_DMA3_CCR(id)); in stm32_dma3_chan_start()
771 writel_relaxed(ccr | CCR_EN, ddata->base + STM32_DMA3_CCR(id)); in stm32_dma3_chan_start()
781 u32 csr, ccr = readl_relaxed(ddata->base + STM32_DMA3_CCR(chan->id)) & ~CCR_EN; in stm32_dma3_chan_suspend()
789 writel_relaxed(ccr, ddata->base + STM32_DMA3_CCR(chan->id)); in stm32_dma3_chan_suspend()
806 u32 ccr = readl_relaxed(ddata->base + STM32_DMA3_CCR(chan->id)) & ~CCR_EN; in stm32_dma3_chan_reset()
808 writel_relaxed(ccr |= CCR_RESET, ddata->base + STM32_DMA3_CCR(chan->id)); in stm32_dma3_chan_reset()
848 writel_relaxed(swdesc->ccr | CCR_SUSP, ddata->base + STM32_DMA3_CCR(chan->id)); in stm32_dma3_chan_set_residue()
854 writel_relaxed(swdesc->ccr, ddata->base + STM32_DMA3_CCR(chan->id)); in stm32_dma3_chan_set_residue()
879 writel_relaxed(swdesc->ccr, ddata->base + STM32_DMA3_CCR(chan->id)); in stm32_dma3_chan_set_residue()
948 ccr = readl_relaxed(ddata->base + STM32_DMA3_CCR(chan->id)); in stm32_dma3_chan_stop()
949 writel_relaxed(ccr & ~(CCR_ALLIE | CCR_EN), ddata->base + STM32_DMA3_CCR(chan->id)); in stm32_dma3_chan_stop()
992 ccr = readl_relaxed(ddata->base + STM32_DMA3_CCR(chan->id)) & CCR_ALLIE; in stm32_dma3_chan_irq()