176 	u32 dma_scr;  member
386 	chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;  in stm32_dma_set_fifo_config()
390 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;  in stm32_dma_set_fifo_config()
450 	u32 dma_scr, id, reg;  in stm32_dma_disable_chan()  local
454 	dma_scr = stm32_dma_read(dmadev, reg);  in stm32_dma_disable_chan()
456 	if (dma_scr & STM32_DMA_SCR_EN) {  in stm32_dma_disable_chan()
457 		dma_scr &= ~STM32_DMA_SCR_EN;  in stm32_dma_disable_chan()
458 		stm32_dma_write(dmadev, reg, dma_scr);  in stm32_dma_disable_chan()
461 					dma_scr, !(dma_scr & STM32_DMA_SCR_EN),  in stm32_dma_disable_chan()
471 	u32 dma_scr, dma_sfcr, status;  in stm32_dma_stop()  local
475 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_stop()
476 	dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;  in stm32_dma_stop()
477 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_stop()
588 		reg->dma_scr &= ~STM32_DMA_SCR_TCIE;  in stm32_dma_start_transfer()
590 	reg->dma_scr &= ~STM32_DMA_SCR_EN;  in stm32_dma_start_transfer()
591 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);  in stm32_dma_start_transfer()
613 	reg->dma_scr |= STM32_DMA_SCR_EN;  in stm32_dma_start_transfer()
614 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);  in stm32_dma_start_transfer()
623 	u32 dma_scr, dma_sm0ar, dma_sm1ar, id;  in stm32_dma_configure_next_sg()  local
626 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));  in stm32_dma_configure_next_sg()
630 	if (dma_scr & STM32_DMA_SCR_CT) {  in stm32_dma_configure_next_sg()
646 	u32 dma_scr;  in stm32_dma_handle_chan_paused()  local
652 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_handle_chan_paused()
660 			dma_scr |= STM32_DMA_SCR_CIRC;  in stm32_dma_handle_chan_paused()
662 			dma_scr |= STM32_DMA_SCR_DBM;  in stm32_dma_handle_chan_paused()
664 	chan->chan_reg.dma_scr = dma_scr;  in stm32_dma_handle_chan_paused()
671 		dma_scr &= ~(STM32_DMA_SCR_DBM | STM32_DMA_SCR_CIRC);  in stm32_dma_handle_chan_paused()
672 		stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_handle_chan_paused()
686 	u32 dma_scr, status, id;  in stm32_dma_post_resume_reconfigure()  local
689 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));  in stm32_dma_post_resume_reconfigure()
712 	if (chan->chan_reg.dma_scr & STM32_DMA_SCR_DBM) {  in stm32_dma_post_resume_reconfigure()
713 		dma_scr |= STM32_DMA_SCR_DBM;  in stm32_dma_post_resume_reconfigure()
715 		if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CT)  in stm32_dma_post_resume_reconfigure()
716 			dma_scr &= ~STM32_DMA_SCR_CT;  in stm32_dma_post_resume_reconfigure()
718 			dma_scr |= STM32_DMA_SCR_CT;  in stm32_dma_post_resume_reconfigure()
719 	} else if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CIRC) {  in stm32_dma_post_resume_reconfigure()
720 		dma_scr |= STM32_DMA_SCR_CIRC;  in stm32_dma_post_resume_reconfigure()
722 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_post_resume_reconfigure()
728 	dma_scr |= STM32_DMA_SCR_EN;  in stm32_dma_post_resume_reconfigure()
729 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_post_resume_reconfigure()
876 	offset <<= FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, chan_reg.dma_scr);  in stm32_dma_resume()
885 	if (chan_reg.dma_scr & STM32_DMA_SCR_PINC)  in stm32_dma_resume()
890 	if (!(chan_reg.dma_scr & STM32_DMA_SCR_MINC))  in stm32_dma_resume()
898 	if ((chan_reg.dma_scr & STM32_DMA_SCR_DBM) && (chan_reg.dma_scr & STM32_DMA_SCR_CT))  in stm32_dma_resume()
910 	if (chan_reg.dma_scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM))  in stm32_dma_resume()
911 		chan_reg.dma_scr &= ~(STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM);  in stm32_dma_resume()
913 	if (chan_reg.dma_scr & STM32_DMA_SCR_DBM)  in stm32_dma_resume()
920 	chan_reg.dma_scr |= STM32_DMA_SCR_EN;  in stm32_dma_resume()
921 	stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);  in stm32_dma_resume()
939 	u32 dma_scr, fifoth;  in stm32_dma_set_xfer_param()  local
988 		dma_scr = FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_MEM_TO_DEV) |  in stm32_dma_set_xfer_param()
1045 		dma_scr = FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_DEV_TO_MEM) |  in stm32_dma_set_xfer_param()
1069 	chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |  in stm32_dma_set_xfer_param()
1072 	chan->chan_reg.dma_scr |= dma_scr;  in stm32_dma_set_xfer_param()
1111 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_slave_sg()
1113 		chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_slave_sg()
1117 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;  in stm32_dma_prep_slave_sg()
1118 		chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;  in stm32_dma_prep_slave_sg()
1137 		desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;  in stm32_dma_prep_slave_sg()
1205 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;  in stm32_dma_prep_dma_cyclic()
1207 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;  in stm32_dma_prep_dma_cyclic()
1208 		chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;  in stm32_dma_prep_dma_cyclic()
1212 	chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_dma_cyclic()
1225 		desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;  in stm32_dma_prep_dma_cyclic()
1275 		desc->sg_req[i].chan_reg.dma_scr =  in stm32_dma_prep_dma_memcpy()
1297 	u32 dma_scr, width, ndtr;  in stm32_dma_get_remaining_bytes()  local
1300 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_get_remaining_bytes()
1301 	width = FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, dma_scr);  in stm32_dma_get_remaining_bytes()
1323 	u32 dma_scr, dma_smar, id, period_len;  in stm32_dma_is_current_sg()  local
1326 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));  in stm32_dma_is_current_sg()
1329 	if (!(dma_scr & STM32_DMA_SCR_DBM))  in stm32_dma_is_current_sg()
1336 	if (dma_scr & STM32_DMA_SCR_CT) {  in stm32_dma_is_current_sg()
1507 	chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;  in stm32_dma_set_config()
1508 	chan->chan_reg.dma_scr |= FIELD_PREP(STM32_DMA_SCR_REQ_MASK, cfg->request_line);  in stm32_dma_set_config()
1511 	chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;  in stm32_dma_set_config()
1517 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF;  in stm32_dma_set_config()