Lines Matching defs:virtbase

552  * @virtbase: The virtual base address of the DMA's register.
595 	void __iomem			 *virtbase;
643 	return chan->base->virtbase + D40_DREG_PCBASE +
1080 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1082 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1297 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1299 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1381 	writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1386 	writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1675 		regs[i] = readl(base->virtbase + il[i].src);
1703 		writel(BIT(idx), base->virtbase + il[row].clr);
2078 			active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2080 			active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2337 	writel(bit, d40c->base->virtbase + prioreg + group * 4);
2338 	writel(bit, d40c->base->virtbase + rtreg + group * 4);
2974 		addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
2984 	dma40_backup(base->virtbase, base->reg_val_backup,
2990 		dma40_backup(base->virtbase, base->reg_val_backup_v4,
3005 			       base->virtbase + D40_DREG_GCC);
3017 		       base->virtbase + D40_DREG_GCC);
3039 	val[0] = readl(base->virtbase + D40_DREG_PRSME);
3040 	val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3090 	val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3109 	writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3129 	void __iomem *virtbase;
3146 	virtbase = devm_platform_ioremap_resource_byname(pdev, "base");
3147 	if (IS_ERR(virtbase))
3148 		return PTR_ERR(virtbase);
3152 		pid |= (readl(virtbase + SZ_4K - 0x20 + 4 * i)
3155 		cid |= (readl(virtbase + SZ_4K - 0x10 + 4 * i)
3187 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3216 	base->virtbase = virtbase;
3317 		       base->virtbase + dma_init_reg[i].reg);
3342 	writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3343 	writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3344 	writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3345 	writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3348 	writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3351 	writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3434 	       base->virtbase + D40_DREG_LCLA);
3539 	val = readl(base->virtbase + D40_DREG_LCPA);
3545 		writel(base->phy_lcpa, base->virtbase + D40_DREG_LCPA);
3570 		writel(res->start, base->virtbase + D40_DREG_LCLA);
3614 	writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);