Lines Matching +full:dual +full:- +full:direction
1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
28 #include <linux/dma-mapping.h>
39 #include <linux/dma/imx-dma.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
45 #include "virt-dma.h"
130 * 0-7 Lower WML Lower watermark level
141 * 13 Source FIFO 1: Source is dual FIFO
143 * 14 Destination FIFO 1: Destination is dual FIFO
145 * 15 --------- MUST BE 0
146 * 16-23 Higher WML HWML
147 * 24-27 N Total number of samples after
158 * 30 --------- MUST BE 0
201 * struct sdma_script_start_addrs - SDMA script start pointers
263 * Mode/Count of data node descriptors - IPCv2
282 * struct sdma_channel_control - Channel control Block
296 * struct sdma_state_registers - SDMA context for a channel
325 * struct sdma_context_data - sdma context specific to a channel
383 * struct sdma_desc - descriptor structor for one transfer
390 * @chn_real_count: the real count updated from bd->mode.count
409 * struct sdma_channel - housekeeping for a SDMA channel
415 * @direction: transfer type. Needed for setting SDMA script
451 enum dma_transfer_direction direction; member
488 * struct sdma_firmware_header - Layout of the firmware image
550 enum dma_transfer_direction direction);
675 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
676 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
677 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
678 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
679 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
680 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
681 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
682 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
683 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
689 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
695 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
702 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership()
703 int channel = sdmac->channel; in sdma_config_ownership()
707 return -EINVAL; in sdma_config_ownership()
709 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
710 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
711 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
728 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
729 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
730 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
737 return !!(readl(sdma->regs + SDMA_H_STATSTOP) & BIT(channel)); in is_sdma_channel_enabled()
742 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
746 * sdma_run_channel0 - run a channel and wait till it's done
755 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
758 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
761 reg = readl(sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
764 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
773 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
779 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); in sdma_load_script()
781 return -ENOMEM; in sdma_load_script()
783 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
785 bd0->mode.command = C0_SETPM; in sdma_load_script()
786 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_script()
787 bd0->mode.count = size / 2; in sdma_load_script()
788 bd0->buffer_addr = buf_phys; in sdma_load_script()
789 bd0->ext_buffer_addr = address; in sdma_load_script()
795 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
797 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); in sdma_load_script()
804 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable()
805 int channel = sdmac->channel; in sdma_event_enable()
809 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
811 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
814 if (sdmac->sw_done) { in sdma_event_enable()
815 val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
818 writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
824 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable()
825 int channel = sdmac->channel; in sdma_event_disable()
829 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
831 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
841 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); in sdma_start_desc()
843 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc()
844 int channel = sdmac->channel; in sdma_start_desc()
847 sdmac->desc = NULL; in sdma_start_desc()
850 sdmac->desc = desc = to_sdma_desc(&vd->tx); in sdma_start_desc()
852 list_del(&vd->node); in sdma_start_desc()
854 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
855 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
856 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
863 enum dma_status old_status = sdmac->status; in sdma_update_channel_loop()
866 * loop mode. Iterate over descriptors, re-setup them and in sdma_update_channel_loop()
869 while (sdmac->desc) { in sdma_update_channel_loop()
870 struct sdma_desc *desc = sdmac->desc; in sdma_update_channel_loop()
872 bd = &desc->bd[desc->buf_tail]; in sdma_update_channel_loop()
874 if (bd->mode.status & BD_DONE) in sdma_update_channel_loop()
877 if (bd->mode.status & BD_RROR) { in sdma_update_channel_loop()
878 bd->mode.status &= ~BD_RROR; in sdma_update_channel_loop()
879 sdmac->status = DMA_ERROR; in sdma_update_channel_loop()
880 error = -EIO; in sdma_update_channel_loop()
884 * We use bd->mode.count to calculate the residue, since contains in sdma_update_channel_loop()
888 desc->chn_real_count = bd->mode.count; in sdma_update_channel_loop()
889 bd->mode.count = desc->period_len; in sdma_update_channel_loop()
890 desc->buf_ptail = desc->buf_tail; in sdma_update_channel_loop()
891 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; in sdma_update_channel_loop()
899 spin_unlock(&sdmac->vc.lock); in sdma_update_channel_loop()
900 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); in sdma_update_channel_loop()
901 spin_lock(&sdmac->vc.lock); in sdma_update_channel_loop()
904 bd->mode.status |= BD_DONE; in sdma_update_channel_loop()
907 sdmac->status = old_status; in sdma_update_channel_loop()
914 if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) { in sdma_update_channel_loop()
915 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel); in sdma_update_channel_loop()
916 sdma_enable_channel(sdmac->sdma, sdmac->channel); in sdma_update_channel_loop()
926 sdmac->desc->chn_real_count = 0; in mxc_sdma_handle_channel_normal()
931 for (i = 0; i < sdmac->desc->num_bd; i++) { in mxc_sdma_handle_channel_normal()
932 bd = &sdmac->desc->bd[i]; in mxc_sdma_handle_channel_normal()
934 if (bd->mode.status & (BD_DONE | BD_RROR)) in mxc_sdma_handle_channel_normal()
935 error = -EIO; in mxc_sdma_handle_channel_normal()
936 sdmac->desc->chn_real_count += bd->mode.count; in mxc_sdma_handle_channel_normal()
940 sdmac->status = DMA_ERROR; in mxc_sdma_handle_channel_normal()
942 sdmac->status = DMA_COMPLETE; in mxc_sdma_handle_channel_normal()
950 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
951 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
956 int channel = fls(stat) - 1; in sdma_int_handler()
957 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
960 spin_lock(&sdmac->vc.lock); in sdma_int_handler()
961 desc = sdmac->desc; in sdma_int_handler()
963 if (sdmac->flags & IMX_DMA_SG_LOOP) { in sdma_int_handler()
964 if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) in sdma_int_handler()
967 vchan_cyclic_callback(&desc->vd); in sdma_int_handler()
970 vchan_cookie_complete(&desc->vd); in sdma_int_handler()
975 spin_unlock(&sdmac->vc.lock); in sdma_int_handler()
988 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc()
992 * two peripherals or memory-to-memory transfers in sdma_get_pc()
996 sdmac->pc_from_device = 0; in sdma_get_pc()
997 sdmac->pc_to_device = 0; in sdma_get_pc()
998 sdmac->device_to_device = 0; in sdma_get_pc()
999 sdmac->pc_to_pc = 0; in sdma_get_pc()
1000 sdmac->is_ram_script = false; in sdma_get_pc()
1004 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
1007 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
1008 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
1011 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
1012 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
1015 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
1016 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1019 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
1020 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1023 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
1024 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
1027 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1030 if (sdmac->sdma->drvdata->ecspi_fixed) { in sdma_get_pc()
1031 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1033 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; in sdma_get_pc()
1034 sdmac->is_ram_script = true; in sdma_get_pc()
1041 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1042 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1045 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
1046 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
1047 sdmac->is_ram_script = true; in sdma_get_pc()
1055 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1056 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1059 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1060 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1061 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1062 sdmac->is_ram_script = true; in sdma_get_pc()
1065 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1066 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1067 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1070 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
1071 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
1074 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
1077 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
1078 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
1081 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
1084 per_2_emi = sdma->script_addrs->sai_2_mcu_addr; in sdma_get_pc()
1085 emi_2_per = sdma->script_addrs->mcu_2_sai_addr; in sdma_get_pc()
1088 per_2_emi = sdma->script_addrs->i2c_2_mcu_addr; in sdma_get_pc()
1089 emi_2_per = sdma->script_addrs->mcu_2_i2c_addr; in sdma_get_pc()
1090 sdmac->is_ram_script = true; in sdma_get_pc()
1093 emi_2_per = sdma->script_addrs->hdmi_dma_addr; in sdma_get_pc()
1094 sdmac->is_ram_script = true; in sdma_get_pc()
1097 dev_err(sdma->dev, "Unsupported transfer type %d\n", in sdma_get_pc()
1099 return -EINVAL; in sdma_get_pc()
1102 sdmac->pc_from_device = per_2_emi; in sdma_get_pc()
1103 sdmac->pc_to_device = emi_2_per; in sdma_get_pc()
1104 sdmac->device_to_device = per_2_per; in sdma_get_pc()
1105 sdmac->pc_to_pc = emi_2_emi; in sdma_get_pc()
1112 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context()
1113 int channel = sdmac->channel; in sdma_load_context()
1115 struct sdma_context_data *context = sdma->context; in sdma_load_context()
1116 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
1120 if (sdmac->direction == DMA_DEV_TO_MEM) in sdma_load_context()
1121 load_address = sdmac->pc_from_device; in sdma_load_context()
1122 else if (sdmac->direction == DMA_DEV_TO_DEV) in sdma_load_context()
1123 load_address = sdmac->device_to_device; in sdma_load_context()
1124 else if (sdmac->direction == DMA_MEM_TO_MEM) in sdma_load_context()
1125 load_address = sdmac->pc_to_pc; in sdma_load_context()
1127 load_address = sdmac->pc_to_device; in sdma_load_context()
1132 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
1133 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
1134 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
1135 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
1136 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
1137 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
1139 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
1142 context->channel_state.pc = load_address; in sdma_load_context()
1147 if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { in sdma_load_context()
1148 context->gReg[4] = sdmac->per_addr; in sdma_load_context()
1149 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1151 context->gReg[0] = sdmac->event_mask[1]; in sdma_load_context()
1152 context->gReg[1] = sdmac->event_mask[0]; in sdma_load_context()
1153 context->gReg[2] = sdmac->per_addr; in sdma_load_context()
1154 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1155 context->gReg[7] = sdmac->watermark_level; in sdma_load_context()
1158 bd0->mode.command = C0_SETDM; in sdma_load_context()
1159 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_context()
1160 bd0->mode.count = sizeof(*context) / 4; in sdma_load_context()
1161 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1162 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; in sdma_load_context()
1165 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1178 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel()
1179 int channel = sdmac->channel; in sdma_disable_channel()
1181 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1182 sdmac->status = DMA_ERROR; in sdma_disable_channel()
1198 vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated); in sdma_channel_terminate_work()
1206 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_terminate_all()
1210 if (sdmac->desc) { in sdma_terminate_all()
1211 vchan_terminate_vdesc(&sdmac->desc->vd); in sdma_terminate_all()
1218 vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated); in sdma_terminate_all()
1219 sdmac->desc = NULL; in sdma_terminate_all()
1220 schedule_work(&sdmac->terminate_worker); in sdma_terminate_all()
1223 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_terminate_all()
1232 vchan_synchronize(&sdmac->vc); in sdma_channel_synchronize()
1234 flush_work(&sdmac->terminate_worker); in sdma_channel_synchronize()
1239 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p()
1241 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; in sdma_set_watermarklevel_for_p2p()
1242 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; in sdma_set_watermarklevel_for_p2p()
1244 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1245 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); in sdma_set_watermarklevel_for_p2p()
1247 if (sdmac->event_id0 > 31) in sdma_set_watermarklevel_for_p2p()
1248 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; in sdma_set_watermarklevel_for_p2p()
1250 if (sdmac->event_id1 > 31) in sdma_set_watermarklevel_for_p2p()
1251 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; in sdma_set_watermarklevel_for_p2p()
1259 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | in sdma_set_watermarklevel_for_p2p()
1261 sdmac->watermark_level |= hwml; in sdma_set_watermarklevel_for_p2p()
1262 sdmac->watermark_level |= lwml << 16; in sdma_set_watermarklevel_for_p2p()
1263 swap(sdmac->event_mask[0], sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1266 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1267 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1268 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; in sdma_set_watermarklevel_for_p2p()
1270 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1271 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1272 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; in sdma_set_watermarklevel_for_p2p()
1274 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; in sdma_set_watermarklevel_for_p2p()
1277 * Limitation: The p2p script support dual fifos in maximum, in sdma_set_watermarklevel_for_p2p()
1278 * So when fifo number is larger than 1, force enable dual in sdma_set_watermarklevel_for_p2p()
1281 if (sdmac->n_fifos_src > 1) in sdma_set_watermarklevel_for_p2p()
1282 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD; in sdma_set_watermarklevel_for_p2p()
1283 if (sdmac->n_fifos_dst > 1) in sdma_set_watermarklevel_for_p2p()
1284 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD; in sdma_set_watermarklevel_for_p2p()
1293 if (sdmac->sw_done) in sdma_set_watermarklevel_for_sais()
1294 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE; in sdma_set_watermarklevel_for_sais()
1296 if (sdmac->direction == DMA_DEV_TO_MEM) { in sdma_set_watermarklevel_for_sais()
1297 n_fifos = sdmac->n_fifos_src; in sdma_set_watermarklevel_for_sais()
1298 stride_fifos = sdmac->stride_fifos_src; in sdma_set_watermarklevel_for_sais()
1300 n_fifos = sdmac->n_fifos_dst; in sdma_set_watermarklevel_for_sais()
1301 stride_fifos = sdmac->stride_fifos_dst; in sdma_set_watermarklevel_for_sais()
1304 words_per_fifo = sdmac->words_per_fifo; in sdma_set_watermarklevel_for_sais()
1306 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1308 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1311 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1312 FIELD_PREP(SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO, (words_per_fifo - 1)); in sdma_set_watermarklevel_for_sais()
1322 sdmac->event_mask[0] = 0; in sdma_config_channel()
1323 sdmac->event_mask[1] = 0; in sdma_config_channel()
1324 sdmac->shp_addr = 0; in sdma_config_channel()
1325 sdmac->per_addr = 0; in sdma_config_channel()
1327 switch (sdmac->peripheral_type) { in sdma_config_channel()
1339 ret = sdma_get_pc(sdmac, sdmac->peripheral_type); in sdma_config_channel()
1343 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && in sdma_config_channel()
1344 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { in sdma_config_channel()
1346 if (sdmac->event_id1) { in sdma_config_channel()
1347 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || in sdma_config_channel()
1348 sdmac->peripheral_type == IMX_DMATYPE_ASRC) in sdma_config_channel()
1351 if (sdmac->peripheral_type == in sdma_config_channel()
1355 __set_bit(sdmac->event_id0, sdmac->event_mask); in sdma_config_channel()
1359 sdmac->shp_addr = sdmac->per_address; in sdma_config_channel()
1360 sdmac->per_addr = sdmac->per_address2; in sdma_config_channel()
1362 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ in sdma_config_channel()
1371 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority()
1372 int channel = sdmac->channel; in sdma_set_channel_priority()
1376 return -EINVAL; in sdma_set_channel_priority()
1379 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1386 int ret = -EBUSY; in sdma_request_channel0()
1388 if (sdma->iram_pool) in sdma_request_channel0()
1389 sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, in sdma_request_channel0()
1391 &sdma->bd0_phys); in sdma_request_channel0()
1393 sdma->bd0 = dma_alloc_coherent(sdma->dev, in sdma_request_channel0()
1395 &sdma->bd0_phys, GFP_NOWAIT); in sdma_request_channel0()
1396 if (!sdma->bd0) { in sdma_request_channel0()
1397 ret = -ENOMEM; in sdma_request_channel0()
1401 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1402 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1404 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1414 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_alloc_bd()
1415 struct sdma_engine *sdma = desc->sdmac->sdma; in sdma_alloc_bd()
1418 if (sdma->iram_pool) in sdma_alloc_bd()
1419 desc->bd = gen_pool_dma_alloc(sdma->iram_pool, bd_size, &desc->bd_phys); in sdma_alloc_bd()
1421 desc->bd = dma_alloc_coherent(sdma->dev, bd_size, &desc->bd_phys, GFP_NOWAIT); in sdma_alloc_bd()
1423 if (!desc->bd) { in sdma_alloc_bd()
1424 ret = -ENOMEM; in sdma_alloc_bd()
1433 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_free_bd()
1434 struct sdma_engine *sdma = desc->sdmac->sdma; in sdma_free_bd()
1436 if (sdma->iram_pool) in sdma_free_bd()
1437 gen_pool_free(sdma->iram_pool, (unsigned long)desc->bd, bd_size); in sdma_free_bd()
1439 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, desc->bd_phys); in sdma_free_bd()
1453 struct imx_dma_data *data = chan->private; in sdma_alloc_chan_resources()
1458 * MEMCPY may never setup chan->private by filter function such as in sdma_alloc_chan_resources()
1460 * Please note in any other slave case, you have to setup chan->private in sdma_alloc_chan_resources()
1467 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1479 switch (data->priority) { in sdma_alloc_chan_resources()
1492 sdmac->peripheral_type = data->peripheral_type; in sdma_alloc_chan_resources()
1493 sdmac->event_id0 = data->dma_request; in sdma_alloc_chan_resources()
1494 sdmac->event_id1 = data->dma_request2; in sdma_alloc_chan_resources()
1496 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1499 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1510 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1512 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1519 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources()
1525 sdma_event_disable(sdmac, sdmac->event_id0); in sdma_free_chan_resources()
1526 if (sdmac->event_id1) in sdma_free_chan_resources()
1527 sdma_event_disable(sdmac, sdmac->event_id1); in sdma_free_chan_resources()
1529 sdmac->event_id0 = 0; in sdma_free_chan_resources()
1530 sdmac->event_id1 = 0; in sdma_free_chan_resources()
1534 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1535 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1539 enum dma_transfer_direction direction, u32 bds) in sdma_transfer_init() argument
1543 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { in sdma_transfer_init()
1544 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n"); in sdma_transfer_init()
1552 sdmac->status = DMA_IN_PROGRESS; in sdma_transfer_init()
1553 sdmac->direction = direction; in sdma_transfer_init()
1554 sdmac->flags = 0; in sdma_transfer_init()
1556 desc->chn_count = 0; in sdma_transfer_init()
1557 desc->chn_real_count = 0; in sdma_transfer_init()
1558 desc->buf_tail = 0; in sdma_transfer_init()
1559 desc->buf_ptail = 0; in sdma_transfer_init()
1560 desc->sdmac = sdmac; in sdma_transfer_init()
1561 desc->num_bd = bds; in sdma_transfer_init()
1567 if (direction == DMA_MEM_TO_MEM) in sdma_transfer_init()
1588 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy()
1589 int channel = sdmac->channel; in sdma_prep_memcpy()
1598 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1608 bd = &desc->bd[i]; in sdma_prep_memcpy()
1609 bd->buffer_addr = dma_src; in sdma_prep_memcpy()
1610 bd->ext_buffer_addr = dma_dst; in sdma_prep_memcpy()
1611 bd->mode.count = count; in sdma_prep_memcpy()
1612 desc->chn_count += count; in sdma_prep_memcpy()
1613 bd->mode.command = 0; in sdma_prep_memcpy()
1617 len -= count; in sdma_prep_memcpy()
1628 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1629 i, count, bd->buffer_addr, in sdma_prep_memcpy()
1633 bd->mode.status = param; in sdma_prep_memcpy()
1636 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_memcpy()
1641 unsigned int sg_len, enum dma_transfer_direction direction, in sdma_prep_slave_sg() argument
1645 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg()
1647 int channel = sdmac->channel; in sdma_prep_slave_sg()
1651 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_slave_sg()
1653 desc = sdma_transfer_init(sdmac, direction, sg_len); in sdma_prep_slave_sg()
1657 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1661 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_slave_sg()
1664 bd->buffer_addr = sg->dma_address; in sdma_prep_slave_sg()
1669 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1674 bd->mode.count = count; in sdma_prep_slave_sg()
1675 desc->chn_count += count; in sdma_prep_slave_sg()
1677 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_slave_sg()
1680 switch (sdmac->word_size) { in sdma_prep_slave_sg()
1682 bd->mode.command = 0; in sdma_prep_slave_sg()
1683 if (count & 3 || sg->dma_address & 3) in sdma_prep_slave_sg()
1687 bd->mode.command = 3; in sdma_prep_slave_sg()
1690 bd->mode.command = 2; in sdma_prep_slave_sg()
1691 if (count & 1 || sg->dma_address & 1) in sdma_prep_slave_sg()
1695 bd->mode.command = 1; in sdma_prep_slave_sg()
1709 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1710 i, count, (u64)sg->dma_address, in sdma_prep_slave_sg()
1714 bd->mode.status = param; in sdma_prep_slave_sg()
1717 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_slave_sg()
1722 sdmac->status = DMA_ERROR; in sdma_prep_slave_sg()
1728 size_t period_len, enum dma_transfer_direction direction, in sdma_prep_dma_cyclic() argument
1732 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic()
1734 int channel = sdmac->channel; in sdma_prep_dma_cyclic()
1738 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1740 if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) in sdma_prep_dma_cyclic()
1743 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_dma_cyclic()
1745 desc = sdma_transfer_init(sdmac, direction, num_periods); in sdma_prep_dma_cyclic()
1749 desc->period_len = period_len; in sdma_prep_dma_cyclic()
1751 sdmac->flags |= IMX_DMA_SG_LOOP; in sdma_prep_dma_cyclic()
1754 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1759 if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) in sdma_prep_dma_cyclic()
1760 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1763 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_dma_cyclic()
1766 bd->buffer_addr = dma_addr; in sdma_prep_dma_cyclic()
1768 bd->mode.count = period_len; in sdma_prep_dma_cyclic()
1770 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1772 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1773 bd->mode.command = 0; in sdma_prep_dma_cyclic()
1775 bd->mode.command = sdmac->word_size; in sdma_prep_dma_cyclic()
1781 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1786 bd->mode.status = param; in sdma_prep_dma_cyclic()
1794 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1799 sdmac->status = DMA_ERROR; in sdma_prep_dma_cyclic()
1805 enum dma_transfer_direction direction) in sdma_config_write() argument
1809 if (direction == DMA_DEV_TO_MEM) { in sdma_config_write()
1810 sdmac->per_address = dmaengine_cfg->src_addr; in sdma_config_write()
1811 sdmac->watermark_level = dmaengine_cfg->src_maxburst * in sdma_config_write()
1812 dmaengine_cfg->src_addr_width; in sdma_config_write()
1813 sdmac->word_size = dmaengine_cfg->src_addr_width; in sdma_config_write()
1814 } else if (direction == DMA_DEV_TO_DEV) { in sdma_config_write()
1815 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1816 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1817 sdmac->watermark_level = dmaengine_cfg->src_maxburst & in sdma_config_write()
1819 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & in sdma_config_write()
1821 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1822 } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { in sdma_config_write()
1823 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1824 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1825 sdmac->watermark_level = 0; in sdma_config_write()
1827 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1828 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * in sdma_config_write()
1829 dmaengine_cfg->dst_addr_width; in sdma_config_write()
1830 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1832 sdmac->direction = direction; in sdma_config_write()
1840 struct sdma_engine *sdma = sdmac->sdma; in sdma_config()
1842 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); in sdma_config()
1844 if (dmaengine_cfg->peripheral_config) { in sdma_config()
1845 struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config; in sdma_config()
1846 if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) { in sdma_config()
1847 dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n", in sdma_config()
1848 dmaengine_cfg->peripheral_size, in sdma_config()
1850 return -EINVAL; in sdma_config()
1852 sdmac->n_fifos_src = sdmacfg->n_fifos_src; in sdma_config()
1853 sdmac->n_fifos_dst = sdmacfg->n_fifos_dst; in sdma_config()
1854 sdmac->stride_fifos_src = sdmacfg->stride_fifos_src; in sdma_config()
1855 sdmac->stride_fifos_dst = sdmacfg->stride_fifos_dst; in sdma_config()
1856 sdmac->words_per_fifo = sdmacfg->words_per_fifo; in sdma_config()
1857 sdmac->sw_done = sdmacfg->sw_done; in sdma_config()
1861 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1862 return -EINVAL; in sdma_config()
1863 sdma_event_enable(sdmac, sdmac->event_id0); in sdma_config()
1865 if (sdmac->event_id1) { in sdma_config()
1866 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1867 return -EINVAL; in sdma_config()
1868 sdma_event_enable(sdmac, sdmac->event_id1); in sdma_config()
1889 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_tx_status()
1891 vd = vchan_find_desc(&sdmac->vc, cookie); in sdma_tx_status()
1893 desc = to_sdma_desc(&vd->tx); in sdma_tx_status()
1894 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) in sdma_tx_status()
1895 desc = sdmac->desc; in sdma_tx_status()
1898 if (sdmac->flags & IMX_DMA_SG_LOOP) in sdma_tx_status()
1899 residue = (desc->num_bd - desc->buf_ptail) * in sdma_tx_status()
1900 desc->period_len - desc->chn_real_count; in sdma_tx_status()
1902 residue = desc->chn_count - desc->chn_real_count; in sdma_tx_status()
1907 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_tx_status()
1909 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, in sdma_tx_status()
1912 return sdmac->status; in sdma_tx_status()
1920 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_issue_pending()
1921 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) in sdma_issue_pending()
1923 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_issue_pending()
1942 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1946 if (!sdma->script_number) in sdma_add_scripts()
1947 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1949 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1951 dev_err(sdma->dev, in sdma_add_scripts()
1953 sdma->script_number); in sdma_add_scripts()
1957 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1967 if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) { in sdma_add_scripts()
1968 if (addr->uart_2_mcu_rom_addr) in sdma_add_scripts()
1969 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr; in sdma_add_scripts()
1970 if (addr->uartsh_2_mcu_rom_addr) in sdma_add_scripts()
1971 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr; in sdma_add_scripts()
1983 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1988 if (fw->size < sizeof(*header)) in sdma_load_firmware()
1991 header = (struct sdma_firmware_header *)fw->data; in sdma_load_firmware()
1993 if (header->magic != SDMA_FIRMWARE_MAGIC) in sdma_load_firmware()
1995 if (header->ram_code_start + header->ram_code_size > fw->size) in sdma_load_firmware()
1997 switch (header->version_major) { in sdma_load_firmware()
1999 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
2002 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
2005 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
2008 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
2011 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
2015 addr = (void *)header + header->script_addrs_start; in sdma_load_firmware()
2016 ram_code = (void *)header + header->ram_code_start; in sdma_load_firmware()
2018 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
2019 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
2022 header->ram_code_size, in sdma_load_firmware()
2023 addr->ram_code_start_addr); in sdma_load_firmware()
2024 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
2025 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
2029 sdma->fw_loaded = true; in sdma_load_firmware()
2031 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
2032 header->version_major, in sdma_load_firmware()
2033 header->version_minor); in sdma_load_firmware()
2043 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
2047 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
2055 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; in sdma_event_remap()
2057 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
2060 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
2062 ret = -EINVAL; in sdma_event_remap()
2068 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
2076 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2083 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2090 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2110 ret = firmware_request_nowait_nowarn(THIS_MODULE, fw_name, sdma->dev, in sdma_get_firmware()
2122 ret = clk_enable(sdma->clk_ipg); in sdma_init()
2125 ret = clk_enable(sdma->clk_ahb); in sdma_init()
2129 if (sdma->drvdata->check_ratio && in sdma_init()
2130 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) in sdma_init()
2131 sdma->clk_ratio = 1; in sdma_init()
2134 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2139 if (sdma->iram_pool) in sdma_init()
2140 sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, ccbsize, &ccb_phys); in sdma_init()
2142 sdma->channel_control = dma_alloc_coherent(sdma->dev, ccbsize, &ccb_phys, in sdma_init()
2145 if (!sdma->channel_control) { in sdma_init()
2146 ret = -ENOMEM; in sdma_init()
2150 sdma->context = (void *)sdma->channel_control + in sdma_init()
2152 sdma->context_phys = ccb_phys + in sdma_init()
2156 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
2157 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
2161 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
2167 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
2170 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
2173 if (sdma->clk_ratio) in sdma_init()
2174 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2176 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2178 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2181 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
2183 clk_disable(sdma->clk_ipg); in sdma_init()
2184 clk_disable(sdma->clk_ahb); in sdma_init()
2189 clk_disable(sdma->clk_ahb); in sdma_init()
2191 clk_disable(sdma->clk_ipg); in sdma_init()
2192 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
2204 sdmac->data = *data; in sdma_filter_fn()
2205 chan->private = &sdmac->data; in sdma_filter_fn()
2213 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate()
2214 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
2217 if (dma_spec->args_count != 3) in sdma_xlate()
2220 data.dma_request = dma_spec->args[0]; in sdma_xlate()
2221 data.peripheral_type = dma_spec->args[1]; in sdma_xlate()
2222 data.priority = dma_spec->args[2]; in sdma_xlate()
2226 * chan->private will point to the imx_dma_data, and in in sdma_xlate()
2228 * be set to sdmac->event_id1. in sdma_xlate()
2233 ofdma->of_node); in sdma_xlate()
2238 struct device_node *np = pdev->dev.of_node; in sdma_probe()
2248 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in sdma_probe()
2252 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
2254 return -ENOMEM; in sdma_probe()
2256 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
2258 sdma->dev = &pdev->dev; in sdma_probe()
2259 sdma->drvdata = of_device_get_match_data(sdma->dev); in sdma_probe()
2265 sdma->regs = devm_platform_ioremap_resource(pdev, 0); in sdma_probe()
2266 if (IS_ERR(sdma->regs)) in sdma_probe()
2267 return PTR_ERR(sdma->regs); in sdma_probe()
2269 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2270 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2271 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2273 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2274 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2275 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2277 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2281 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2285 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, in sdma_probe()
2286 dev_name(&pdev->dev), sdma); in sdma_probe()
2290 sdma->irq = irq; in sdma_probe()
2292 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2293 if (!sdma->script_addrs) { in sdma_probe()
2294 ret = -ENOMEM; in sdma_probe()
2299 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2300 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) in sdma_probe()
2301 saddr_arr[i] = -EINVAL; in sdma_probe()
2303 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2304 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2305 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2306 dma_cap_set(DMA_PRIVATE, sdma->dma_device.cap_mask); in sdma_probe()
2308 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2311 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2313 sdmac->sdma = sdma; in sdma_probe()
2315 sdmac->channel = i; in sdma_probe()
2316 sdmac->vc.desc_free = sdma_desc_free; in sdma_probe()
2317 INIT_LIST_HEAD(&sdmac->terminated); in sdma_probe()
2318 INIT_WORK(&sdmac->terminate_worker, in sdma_probe()
2326 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2330 sdma->iram_pool = of_gen_pool_get(np, "iram", 0); in sdma_probe()
2331 if (sdma->iram_pool) in sdma_probe()
2332 dev_info(&pdev->dev, "alloc bd from iram.\n"); in sdma_probe()
2343 if (sdma->drvdata->script_addrs) in sdma_probe()
2344 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2346 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2348 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2349 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2350 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2351 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2352 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2353 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2354 sdma->dma_device.device_terminate_all = sdma_terminate_all; in sdma_probe()
2355 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2356 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2357 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2358 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2359 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2360 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2361 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2362 sdma->dma_device.copy_align = 2; in sdma_probe()
2363 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2367 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2369 dev_err(&pdev->dev, "unable to register\n"); in sdma_probe()
2376 dev_err(&pdev->dev, "failed to register controller\n"); in sdma_probe()
2380 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); in sdma_probe()
2383 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2384 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2394 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2397 dev_warn(&pdev->dev, "failed to get firmware name\n"); in sdma_probe()
2401 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); in sdma_probe()
2407 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2409 kfree(sdma->script_addrs); in sdma_probe()
2411 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2413 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2422 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2423 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2424 kfree(sdma->script_addrs); in sdma_remove()
2425 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2426 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2429 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2431 tasklet_kill(&sdmac->vc.task); in sdma_remove()
2432 sdma_free_chan_resources(&sdmac->vc.chan); in sdma_remove()
2440 .name = "imx-sdma",
2452 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2455 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");