1 /* SPDX-License-Identifier: GPL-2.0 */
52 	u64 bits;  member
58 		u64 total_wq_size:16;
72 	u64 bits;  member
86 	u64 bits;  member
95 	u64 bits;  member
104 	u64 bits[4];  member
114 		u64 grpcfg:16;
115 		u64 wqcfg:16;
116 		u64 msix_perm:16;
117 		u64 ims:16;
118 		u64 perfmon:16;
121 	u64 bits[2];  member
135 	u32 bits;  member
146 	u32 bits;  member
156 	u32 bits;  member
190 	u32 bits;  member
220 	u32 bits;  member
283 		u64 batch_idx:16;
284 		u64 rsvd4:16;
291 	u64 bits[4];  member
310 	u64 bits;  member
323 		u64 size:16;
327 	u64 bits[2];  member
341 	u32 bits;  member
359 	u64 bits;  member
370 		/* bytes 0-3 */
374 		/* bytes 4-7 */
378 		/* bytes 8-11 */
389 		/* bytes 12-15 */
394 		/* bytes 16-19 */
399 		/* bytes 20-23 */
404 		/* bytes 24-27 */
411 		/* bytes 28-31 */
414 		/* bytes 32-63 */
417 	u32 bits[16];  member
428  * idxd - struct idxd *
429  * n - wq id
430  * ofs - the index of the 32b dword for the config register
434  * Each register is 32bits. The ofs gives us the number of register to access.
439 	(__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs);	\
442 #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32))
449  * idxd - struct idxd *
450  * n - group id
451  * ofs - the index of the 64b qword for the config register
453  * The GRPCFG register block is divided into three sub-registers, which
455  * to the register block that contains the three sub-registers.
456  * Each register block is 64bits. And the ofs gives us the offset
459 #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
461 #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32)
462 #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40)
472 		u64 global_event_category:16;
481 	u64 bits;  member
490 	u64 bits;  member
576 		u32 head:16;
577 		u32 rsvd:16;
578 		u32 tail:16;
587 	u64 bits;  member