Lines Matching +full:imx93 +full:- +full:edma3
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
12 #include <dt-bindings/dma/fsl-edma.h>
19 #include <linux/dma-mapping.h>
24 #include "fsl-edma-common.h"
30 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
37 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
39 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
43 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
45 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); in fsl_edma_tx_handler()
46 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); in fsl_edma_tx_handler()
72 return fsl_edma_tx_handler(irq, fsl_chan->edma); in fsl_edma2_tx_handler()
79 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_err_handler()
81 err = edma_readl(fsl_edma, regs->errl); in fsl_edma_err_handler()
85 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_err_handler()
87 fsl_edma_disable_request(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
88 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); in fsl_edma_err_handler()
89 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
108 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_srcid_in_use()
109 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_srcid_in_use()
111 if (fsl_chan->srcid && srcid == fsl_chan->srcid) { in fsl_edma_srcid_in_use()
112 dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!"); in fsl_edma_srcid_in_use()
122 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma_xlate()
125 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; in fsl_edma_xlate()
126 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; in fsl_edma_xlate()
128 if (dma_spec->args_count != 2) in fsl_edma_xlate()
131 guard(mutex)(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
133 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
134 if (chan->client_count) in fsl_edma_xlate()
137 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[1])) in fsl_edma_xlate()
140 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { in fsl_edma_xlate()
143 chan->device->privatecnt++; in fsl_edma_xlate()
145 fsl_chan->srcid = dma_spec->args[1]; in fsl_edma_xlate()
147 if (!fsl_chan->srcid) { in fsl_edma_xlate()
148 dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n", in fsl_edma_xlate()
149 fsl_chan->srcid); in fsl_edma_xlate()
153 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, in fsl_edma_xlate()
165 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma3_xlate()
171 if (dma_spec->args_count != 3) in fsl_edma3_xlate()
174 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); in fsl_edma3_xlate()
176 guard(mutex)(&fsl_edma->fsl_edma_mutex); in fsl_edma3_xlate()
177 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, in fsl_edma3_xlate()
180 if (chan->client_count) in fsl_edma3_xlate()
184 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[0])) in fsl_edma3_xlate()
186 i = fsl_chan - fsl_edma->chans; in fsl_edma3_xlate()
188 fsl_chan->priority = dma_spec->args[1]; in fsl_edma3_xlate()
189 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; in fsl_edma3_xlate()
190 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; in fsl_edma3_xlate()
191 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; in fsl_edma3_xlate()
193 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) in fsl_edma3_xlate()
196 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) in fsl_edma3_xlate()
199 if (!b_chmux && i == dma_spec->args[0]) { in fsl_edma3_xlate()
201 chan->device->privatecnt++; in fsl_edma3_xlate()
203 } else if (b_chmux && !fsl_chan->srcid) { in fsl_edma3_xlate()
206 chan->device->privatecnt++; in fsl_edma3_xlate()
207 fsl_chan->srcid = dma_spec->args[0]; in fsl_edma3_xlate()
219 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); in fsl_edma_irq_init()
221 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); in fsl_edma_irq_init()
222 if (fsl_edma->txirq < 0) in fsl_edma_irq_init()
223 return fsl_edma->txirq; in fsl_edma_irq_init()
225 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); in fsl_edma_irq_init()
226 if (fsl_edma->errirq < 0) in fsl_edma_irq_init()
227 return fsl_edma->errirq; in fsl_edma_irq_init()
229 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_init()
230 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
233 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); in fsl_edma_irq_init()
237 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
240 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); in fsl_edma_irq_init()
244 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, in fsl_edma_irq_init()
247 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); in fsl_edma_irq_init()
259 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma3_irq_init()
261 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma3_irq_init()
263 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma3_irq_init()
267 fsl_chan->txirq = platform_get_irq(pdev, i); in fsl_edma3_irq_init()
268 if (fsl_chan->txirq < 0) in fsl_edma3_irq_init()
269 return -EINVAL; in fsl_edma3_irq_init()
271 fsl_chan->irq_handler = fsl_edma3_tx_handler; in fsl_edma3_irq_init()
284 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); in fsl_edma2_irq_init()
287 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); in fsl_edma2_irq_init()
289 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); in fsl_edma2_irq_init()
290 return -EINVAL; in fsl_edma2_irq_init()
302 return -ENXIO; in fsl_edma2_irq_init()
305 if (i == count - 1) { in fsl_edma2_irq_init()
306 ret = devm_request_irq(&pdev->dev, irq, in fsl_edma2_irq_init()
308 0, "eDMA2-ERR", fsl_edma); in fsl_edma2_irq_init()
310 fsl_edma->chans[i].txirq = irq; in fsl_edma2_irq_init()
311 fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler; in fsl_edma2_irq_init()
324 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_exit()
325 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
327 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
328 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); in fsl_edma_irq_exit()
337 clk_disable_unprepare(fsl_edma->muxclk[i]); in fsl_disable_clocks()
408 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
409 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
410 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
411 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
412 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data},
413 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
414 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
415 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5},
425 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma3_detach_pd()
426 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma3_detach_pd()
428 fsl_chan = &fsl_edma->chans[i]; in fsl_edma3_detach_pd()
429 if (fsl_chan->pd_dev_link) in fsl_edma3_detach_pd()
430 device_link_del(fsl_chan->pd_dev_link); in fsl_edma3_detach_pd()
431 if (fsl_chan->pd_dev) { in fsl_edma3_detach_pd()
432 dev_pm_domain_detach(fsl_chan->pd_dev, false); in fsl_edma3_detach_pd()
433 pm_runtime_dont_use_autosuspend(fsl_chan->pd_dev); in fsl_edma3_detach_pd()
434 pm_runtime_set_suspended(fsl_chan->pd_dev); in fsl_edma3_detach_pd()
451 dev = &pdev->dev; in fsl_edma3_attach_pd()
453 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma3_attach_pd()
454 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma3_attach_pd()
457 fsl_chan = &fsl_edma->chans[i]; in fsl_edma3_attach_pd()
465 fsl_chan->pd_dev_link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | in fsl_edma3_attach_pd()
468 if (!fsl_chan->pd_dev_link) { in fsl_edma3_attach_pd()
474 fsl_chan->pd_dev = pd_chan; in fsl_edma3_attach_pd()
476 pm_runtime_use_autosuspend(fsl_chan->pd_dev); in fsl_edma3_attach_pd()
477 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); in fsl_edma3_attach_pd()
478 pm_runtime_set_active(fsl_chan->pd_dev); in fsl_edma3_attach_pd()
485 return -EINVAL; in fsl_edma3_attach_pd()
490 struct device_node *np = pdev->dev.of_node; in fsl_edma_probe()
499 drvdata = device_get_match_data(&pdev->dev); in fsl_edma_probe()
501 dev_err(&pdev->dev, "unable to find driver data\n"); in fsl_edma_probe()
502 return -EINVAL; in fsl_edma_probe()
505 ret = of_property_read_u32(np, "dma-channels", &chans); in fsl_edma_probe()
507 dev_err(&pdev->dev, "Can't get dma-channels.\n"); in fsl_edma_probe()
511 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), in fsl_edma_probe()
514 return -ENOMEM; in fsl_edma_probe()
516 fsl_edma->drvdata = drvdata; in fsl_edma_probe()
517 fsl_edma->n_chans = chans; in fsl_edma_probe()
518 mutex_init(&fsl_edma->fsl_edma_mutex); in fsl_edma_probe()
520 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); in fsl_edma_probe()
521 if (IS_ERR(fsl_edma->membase)) in fsl_edma_probe()
522 return PTR_ERR(fsl_edma->membase); in fsl_edma_probe()
524 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { in fsl_edma_probe()
526 regs = &fsl_edma->regs; in fsl_edma_probe()
529 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { in fsl_edma_probe()
530 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); in fsl_edma_probe()
531 if (IS_ERR(fsl_edma->dmaclk)) { in fsl_edma_probe()
532 dev_err(&pdev->dev, "Missing DMA block clock.\n"); in fsl_edma_probe()
533 return PTR_ERR(fsl_edma->dmaclk); in fsl_edma_probe()
537 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); in fsl_edma_probe()
540 fsl_edma->chan_masked = chan_mask[1]; in fsl_edma_probe()
541 fsl_edma->chan_masked <<= 32; in fsl_edma_probe()
542 fsl_edma->chan_masked |= chan_mask[0]; in fsl_edma_probe()
545 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { in fsl_edma_probe()
549 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) in fsl_edma_probe()
552 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, in fsl_edma_probe()
554 if (IS_ERR(fsl_edma->muxbase[i])) { in fsl_edma_probe()
557 return PTR_ERR(fsl_edma->muxbase[i]); in fsl_edma_probe()
561 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); in fsl_edma_probe()
562 if (IS_ERR(fsl_edma->muxclk[i])) { in fsl_edma_probe()
563 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); in fsl_edma_probe()
565 return PTR_ERR(fsl_edma->muxclk[i]); in fsl_edma_probe()
569 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); in fsl_edma_probe()
571 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { in fsl_edma_probe()
575 ret = devm_add_action_or_reset(&pdev->dev, devm_fsl_edma3_detach_pd, fsl_edma); in fsl_edma_probe()
580 if (drvdata->flags & FSL_EDMA_DRV_TCD64) in fsl_edma_probe()
581 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in fsl_edma_probe()
583 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); in fsl_edma_probe()
584 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_probe()
585 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma_probe()
588 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_probe()
591 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", in fsl_edma_probe()
592 dev_name(&pdev->dev), i); in fsl_edma_probe()
594 fsl_chan->edma = fsl_edma; in fsl_edma_probe()
595 fsl_chan->pm_state = RUNNING; in fsl_edma_probe()
596 fsl_chan->srcid = 0; in fsl_edma_probe()
597 fsl_chan->dma_dir = DMA_NONE; in fsl_edma_probe()
598 fsl_chan->vchan.desc_free = fsl_edma_free_desc; in fsl_edma_probe()
600 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? in fsl_edma_probe()
602 fsl_chan->tcd = fsl_edma->membase in fsl_edma_probe()
603 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; in fsl_edma_probe()
604 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; in fsl_edma_probe()
606 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { in fsl_edma_probe()
608 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, in fsl_edma_probe()
611 if (IS_ERR(fsl_chan->clk)) in fsl_edma_probe()
612 return PTR_ERR(fsl_chan->clk); in fsl_edma_probe()
614 fsl_chan->pdev = pdev; in fsl_edma_probe()
615 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); in fsl_edma_probe()
619 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) in fsl_edma_probe()
620 clk_disable_unprepare(fsl_chan->clk); in fsl_edma_probe()
623 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); in fsl_edma_probe()
627 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
628 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
629 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
630 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
632 fsl_edma->dma_dev.dev = &pdev->dev; in fsl_edma_probe()
633 fsl_edma->dma_dev.device_alloc_chan_resources in fsl_edma_probe()
635 fsl_edma->dma_dev.device_free_chan_resources in fsl_edma_probe()
637 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; in fsl_edma_probe()
638 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; in fsl_edma_probe()
639 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; in fsl_edma_probe()
640 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; in fsl_edma_probe()
641 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; in fsl_edma_probe()
642 fsl_edma->dma_dev.device_pause = fsl_edma_pause; in fsl_edma_probe()
643 fsl_edma->dma_dev.device_resume = fsl_edma_resume; in fsl_edma_probe()
644 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; in fsl_edma_probe()
645 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; in fsl_edma_probe()
646 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; in fsl_edma_probe()
648 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
649 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
651 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { in fsl_edma_probe()
652 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); in fsl_edma_probe()
653 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); in fsl_edma_probe()
656 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in fsl_edma_probe()
657 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) in fsl_edma_probe()
658 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); in fsl_edma_probe()
660 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? in fsl_edma_probe()
665 dma_set_max_seg_size(fsl_edma->dma_dev.dev, in fsl_edma_probe()
668 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in fsl_edma_probe()
672 ret = dma_async_device_register(&fsl_edma->dma_dev); in fsl_edma_probe()
674 dev_err(&pdev->dev, in fsl_edma_probe()
680 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate, in fsl_edma_probe()
683 dev_err(&pdev->dev, in fsl_edma_probe()
685 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_probe()
690 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) in fsl_edma_probe()
691 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_probe()
698 struct device_node *np = pdev->dev.of_node; in fsl_edma_remove()
702 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); in fsl_edma_remove()
704 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_remove()
705 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_remove()
715 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_suspend_late()
716 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_suspend_late()
717 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_suspend_late()
719 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_suspend_late()
721 if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) { in fsl_edma_suspend_late()
722 dev_warn(dev, "WARN: There is non-idle channel."); in fsl_edma_suspend_late()
727 fsl_chan->pm_state = SUSPENDED; in fsl_edma_suspend_late()
728 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_suspend_late()
738 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_resume_early()
741 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_resume_early()
742 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_resume_early()
743 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_resume_early()
745 fsl_chan->pm_state = RUNNING; in fsl_edma_resume_early()
747 if (fsl_chan->srcid != 0) in fsl_edma_resume_early()
748 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true); in fsl_edma_resume_early()
751 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) in fsl_edma_resume_early()
752 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_resume_early()
769 .name = "fsl-edma",
789 MODULE_ALIAS("platform:fsl-edma");