Lines Matching +full:imx7ulp +full:- +full:edma
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
8 * Driver for the Freescale eDMA engine with flexible channel multiplexing
9 * capability for DMA request sources. The eDMA block can be found on some
13 #include <dt-bindings/dma/fsl-edma.h>
20 #include <linux/dma-mapping.h>
25 #include "fsl-edma-common.h"
31 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
38 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
40 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
44 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
46 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); in fsl_edma_tx_handler()
47 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); in fsl_edma_tx_handler()
73 return fsl_edma_tx_handler(irq, fsl_chan->edma); in fsl_edma2_tx_handler()
83 end = min(end, fsl_edma->n_chans); in fsl_edma3_or_tx_handler()
86 chan = &fsl_edma->chans[i]; in fsl_edma3_or_tx_handler()
107 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma3_or_err_handler()
111 err = edma_readl(fsl_edma, regs->es); in fsl_edma3_or_err_handler()
115 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma3_or_err_handler()
116 chan = &fsl_edma->chans[ch]; in fsl_edma3_or_err_handler()
124 fsl_edma->chans[ch].status = DMA_ERROR; in fsl_edma3_or_err_handler()
134 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_err_handler()
136 err = edma_readl(fsl_edma, regs->errl); in fsl_edma_err_handler()
140 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_err_handler()
142 fsl_edma_disable_request(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
143 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); in fsl_edma_err_handler()
144 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
163 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_srcid_in_use()
164 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_srcid_in_use()
166 if (fsl_chan->srcid && srcid == fsl_chan->srcid) { in fsl_edma_srcid_in_use()
167 dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!"); in fsl_edma_srcid_in_use()
177 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma_xlate()
180 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; in fsl_edma_xlate()
181 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; in fsl_edma_xlate()
183 if (dma_spec->args_count != 2) in fsl_edma_xlate()
186 guard(mutex)(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
188 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
189 if (chan->client_count) in fsl_edma_xlate()
192 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[1])) in fsl_edma_xlate()
195 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { in fsl_edma_xlate()
198 chan->device->privatecnt++; in fsl_edma_xlate()
200 fsl_chan->srcid = dma_spec->args[1]; in fsl_edma_xlate()
202 if (!fsl_chan->srcid) { in fsl_edma_xlate()
203 dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n", in fsl_edma_xlate()
204 fsl_chan->srcid); in fsl_edma_xlate()
208 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, in fsl_edma_xlate()
220 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma3_xlate()
226 if (dma_spec->args_count != 3) in fsl_edma3_xlate()
229 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); in fsl_edma3_xlate()
231 guard(mutex)(&fsl_edma->fsl_edma_mutex); in fsl_edma3_xlate()
232 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, in fsl_edma3_xlate()
235 if (chan->client_count) in fsl_edma3_xlate()
239 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[0])) in fsl_edma3_xlate()
241 i = fsl_chan - fsl_edma->chans; in fsl_edma3_xlate()
243 fsl_chan->priority = dma_spec->args[1]; in fsl_edma3_xlate()
244 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; in fsl_edma3_xlate()
245 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; in fsl_edma3_xlate()
246 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; in fsl_edma3_xlate()
248 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) in fsl_edma3_xlate()
251 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) in fsl_edma3_xlate()
254 if (!b_chmux && i == dma_spec->args[0]) { in fsl_edma3_xlate()
256 chan->device->privatecnt++; in fsl_edma3_xlate()
258 } else if (b_chmux && !fsl_chan->srcid) { in fsl_edma3_xlate()
261 chan->device->privatecnt++; in fsl_edma3_xlate()
262 fsl_chan->srcid = dma_spec->args[0]; in fsl_edma3_xlate()
274 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); in fsl_edma_irq_init()
276 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); in fsl_edma_irq_init()
277 if (fsl_edma->txirq < 0) in fsl_edma_irq_init()
278 return fsl_edma->txirq; in fsl_edma_irq_init()
280 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); in fsl_edma_irq_init()
281 if (fsl_edma->errirq < 0) in fsl_edma_irq_init()
282 return fsl_edma->errirq; in fsl_edma_irq_init()
284 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_init()
285 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
286 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); in fsl_edma_irq_init()
288 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); in fsl_edma_irq_init()
292 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
293 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); in fsl_edma_irq_init()
295 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); in fsl_edma_irq_init()
299 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, in fsl_edma_irq_init()
300 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); in fsl_edma_irq_init()
302 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); in fsl_edma_irq_init()
314 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma3_irq_init()
316 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma3_irq_init()
318 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma3_irq_init()
322 fsl_chan->txirq = platform_get_irq(pdev, i); in fsl_edma3_irq_init()
323 if (fsl_chan->txirq < 0) in fsl_edma3_irq_init()
324 return -EINVAL; in fsl_edma3_irq_init()
326 fsl_chan->irq_handler = fsl_edma3_tx_handler; in fsl_edma3_irq_init()
337 fsl_edma->txirq = platform_get_irq_byname(pdev, "tx-0-15"); in fsl_edma3_or_irq_init()
338 if (fsl_edma->txirq < 0) in fsl_edma3_or_irq_init()
339 return fsl_edma->txirq; in fsl_edma3_or_irq_init()
341 fsl_edma->txirq_16_31 = platform_get_irq_byname(pdev, "tx-16-31"); in fsl_edma3_or_irq_init()
342 if (fsl_edma->txirq_16_31 < 0) in fsl_edma3_or_irq_init()
343 return fsl_edma->txirq_16_31; in fsl_edma3_or_irq_init()
345 fsl_edma->errirq = platform_get_irq_byname(pdev, "err"); in fsl_edma3_or_irq_init()
346 if (fsl_edma->errirq < 0) in fsl_edma3_or_irq_init()
347 return fsl_edma->errirq; in fsl_edma3_or_irq_init()
349 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma3_or_irq_init()
350 fsl_edma3_tx_0_15_handler, 0, "eDMA tx0_15", in fsl_edma3_or_irq_init()
353 return dev_err_probe(&pdev->dev, ret, in fsl_edma3_or_irq_init()
354 "Can't register eDMA tx0_15 IRQ.\n"); in fsl_edma3_or_irq_init()
356 if (fsl_edma->n_chans > 16) { in fsl_edma3_or_irq_init()
357 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq_16_31, in fsl_edma3_or_irq_init()
359 "eDMA tx16_31", fsl_edma); in fsl_edma3_or_irq_init()
361 return dev_err_probe(&pdev->dev, ret, in fsl_edma3_or_irq_init()
362 "Can't register eDMA tx16_31 IRQ.\n"); in fsl_edma3_or_irq_init()
365 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, in fsl_edma3_or_irq_init()
366 fsl_edma3_or_err_handler, 0, "eDMA err", in fsl_edma3_or_irq_init()
369 return dev_err_probe(&pdev->dev, ret, in fsl_edma3_or_irq_init()
370 "Can't register eDMA err IRQ.\n"); in fsl_edma3_or_irq_init()
382 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); in fsl_edma2_irq_init()
385 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); in fsl_edma2_irq_init()
387 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); in fsl_edma2_irq_init()
388 return -EINVAL; in fsl_edma2_irq_init()
400 return -ENXIO; in fsl_edma2_irq_init()
402 /* The last IRQ is for eDMA err */ in fsl_edma2_irq_init()
403 if (i == count - 1) { in fsl_edma2_irq_init()
404 ret = devm_request_irq(&pdev->dev, irq, in fsl_edma2_irq_init()
406 0, "eDMA2-ERR", fsl_edma); in fsl_edma2_irq_init()
408 fsl_edma->chans[i].txirq = irq; in fsl_edma2_irq_init()
409 fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler; in fsl_edma2_irq_init()
422 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_exit()
423 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
425 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
426 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); in fsl_edma_irq_exit()
435 clk_disable_unprepare(fsl_edma->muxclk[i]); in fsl_disable_clocks()
514 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
515 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
516 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
517 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
518 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data},
519 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
520 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
521 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5},
522 { .compatible = "nxp,s32g2-edma", .data = &s32g2_data},
532 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma3_detach_pd()
533 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma3_detach_pd()
535 fsl_chan = &fsl_edma->chans[i]; in fsl_edma3_detach_pd()
536 if (fsl_chan->pd_dev_link) in fsl_edma3_detach_pd()
537 device_link_del(fsl_chan->pd_dev_link); in fsl_edma3_detach_pd()
538 if (fsl_chan->pd_dev) { in fsl_edma3_detach_pd()
539 dev_pm_domain_detach(fsl_chan->pd_dev, false); in fsl_edma3_detach_pd()
540 pm_runtime_dont_use_autosuspend(fsl_chan->pd_dev); in fsl_edma3_detach_pd()
541 pm_runtime_set_suspended(fsl_chan->pd_dev); in fsl_edma3_detach_pd()
558 dev = &pdev->dev; in fsl_edma3_attach_pd()
560 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma3_attach_pd()
561 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma3_attach_pd()
564 fsl_chan = &fsl_edma->chans[i]; in fsl_edma3_attach_pd()
572 fsl_chan->pd_dev_link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | in fsl_edma3_attach_pd()
575 if (!fsl_chan->pd_dev_link) { in fsl_edma3_attach_pd()
581 fsl_chan->pd_dev = pd_chan; in fsl_edma3_attach_pd()
583 pm_runtime_use_autosuspend(fsl_chan->pd_dev); in fsl_edma3_attach_pd()
584 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); in fsl_edma3_attach_pd()
585 pm_runtime_set_active(fsl_chan->pd_dev); in fsl_edma3_attach_pd()
592 return -EINVAL; in fsl_edma3_attach_pd()
597 struct device_node *np = pdev->dev.of_node; in fsl_edma_probe()
606 drvdata = device_get_match_data(&pdev->dev); in fsl_edma_probe()
608 dev_err(&pdev->dev, "unable to find driver data\n"); in fsl_edma_probe()
609 return -EINVAL; in fsl_edma_probe()
612 ret = of_property_read_u32(np, "dma-channels", &chans); in fsl_edma_probe()
614 dev_err(&pdev->dev, "Can't get dma-channels.\n"); in fsl_edma_probe()
618 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), in fsl_edma_probe()
621 return -ENOMEM; in fsl_edma_probe()
623 fsl_edma->drvdata = drvdata; in fsl_edma_probe()
624 fsl_edma->n_chans = chans; in fsl_edma_probe()
625 mutex_init(&fsl_edma->fsl_edma_mutex); in fsl_edma_probe()
627 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); in fsl_edma_probe()
628 if (IS_ERR(fsl_edma->membase)) in fsl_edma_probe()
629 return PTR_ERR(fsl_edma->membase); in fsl_edma_probe()
631 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { in fsl_edma_probe()
633 regs = &fsl_edma->regs; in fsl_edma_probe()
636 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { in fsl_edma_probe()
637 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); in fsl_edma_probe()
638 if (IS_ERR(fsl_edma->dmaclk)) { in fsl_edma_probe()
639 dev_err(&pdev->dev, "Missing DMA block clock.\n"); in fsl_edma_probe()
640 return PTR_ERR(fsl_edma->dmaclk); in fsl_edma_probe()
644 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); in fsl_edma_probe()
647 fsl_edma->chan_masked = chan_mask[1]; in fsl_edma_probe()
648 fsl_edma->chan_masked <<= 32; in fsl_edma_probe()
649 fsl_edma->chan_masked |= chan_mask[0]; in fsl_edma_probe()
652 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { in fsl_edma_probe()
655 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, in fsl_edma_probe()
657 if (IS_ERR(fsl_edma->muxbase[i])) { in fsl_edma_probe()
660 return PTR_ERR(fsl_edma->muxbase[i]); in fsl_edma_probe()
664 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); in fsl_edma_probe()
665 if (IS_ERR(fsl_edma->muxclk[i])) { in fsl_edma_probe()
666 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); in fsl_edma_probe()
668 return PTR_ERR(fsl_edma->muxclk[i]); in fsl_edma_probe()
672 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); in fsl_edma_probe()
674 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { in fsl_edma_probe()
678 ret = devm_add_action_or_reset(&pdev->dev, devm_fsl_edma3_detach_pd, fsl_edma); in fsl_edma_probe()
683 if (drvdata->flags & FSL_EDMA_DRV_TCD64) in fsl_edma_probe()
684 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in fsl_edma_probe()
686 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); in fsl_edma_probe()
687 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_probe()
688 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma_probe()
691 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_probe()
694 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", in fsl_edma_probe()
695 dev_name(&pdev->dev), i); in fsl_edma_probe()
697 fsl_chan->edma = fsl_edma; in fsl_edma_probe()
698 fsl_chan->pm_state = RUNNING; in fsl_edma_probe()
699 fsl_chan->srcid = 0; in fsl_edma_probe()
700 fsl_chan->dma_dir = DMA_NONE; in fsl_edma_probe()
701 fsl_chan->vchan.desc_free = fsl_edma_free_desc; in fsl_edma_probe()
703 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? in fsl_edma_probe()
705 fsl_chan->tcd = fsl_edma->membase in fsl_edma_probe()
706 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; in fsl_edma_probe()
707 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; in fsl_edma_probe()
709 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { in fsl_edma_probe()
711 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, in fsl_edma_probe()
714 if (IS_ERR(fsl_chan->clk)) in fsl_edma_probe()
715 return PTR_ERR(fsl_chan->clk); in fsl_edma_probe()
717 fsl_chan->pdev = pdev; in fsl_edma_probe()
718 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); in fsl_edma_probe()
722 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) in fsl_edma_probe()
723 clk_disable_unprepare(fsl_chan->clk); in fsl_edma_probe()
726 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); in fsl_edma_probe()
730 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
731 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
732 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
733 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
735 fsl_edma->dma_dev.dev = &pdev->dev; in fsl_edma_probe()
736 fsl_edma->dma_dev.device_alloc_chan_resources in fsl_edma_probe()
738 fsl_edma->dma_dev.device_free_chan_resources in fsl_edma_probe()
740 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; in fsl_edma_probe()
741 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; in fsl_edma_probe()
742 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; in fsl_edma_probe()
743 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; in fsl_edma_probe()
744 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; in fsl_edma_probe()
745 fsl_edma->dma_dev.device_pause = fsl_edma_pause; in fsl_edma_probe()
746 fsl_edma->dma_dev.device_resume = fsl_edma_resume; in fsl_edma_probe()
747 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; in fsl_edma_probe()
748 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; in fsl_edma_probe()
749 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; in fsl_edma_probe()
751 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
752 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
754 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { in fsl_edma_probe()
755 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); in fsl_edma_probe()
756 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); in fsl_edma_probe()
759 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in fsl_edma_probe()
760 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) in fsl_edma_probe()
761 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); in fsl_edma_probe()
763 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? in fsl_edma_probe()
768 dma_set_max_seg_size(fsl_edma->dma_dev.dev, in fsl_edma_probe()
771 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in fsl_edma_probe()
775 ret = dma_async_device_register(&fsl_edma->dma_dev); in fsl_edma_probe()
777 dev_err(&pdev->dev, in fsl_edma_probe()
778 "Can't register Freescale eDMA engine. (%d)\n", ret); in fsl_edma_probe()
783 drvdata->dmamuxs ? fsl_edma_xlate : fsl_edma3_xlate, in fsl_edma_probe()
786 dev_err(&pdev->dev, in fsl_edma_probe()
787 "Can't register Freescale eDMA of_dma. (%d)\n", ret); in fsl_edma_probe()
788 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_probe()
793 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) in fsl_edma_probe()
794 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_probe()
801 struct device_node *np = pdev->dev.of_node; in fsl_edma_remove()
805 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); in fsl_edma_remove()
807 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_remove()
808 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_remove()
818 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_suspend_late()
819 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_suspend_late()
820 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_suspend_late()
822 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_suspend_late()
824 if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) { in fsl_edma_suspend_late()
825 dev_warn(dev, "WARN: There is non-idle channel."); in fsl_edma_suspend_late()
830 fsl_chan->pm_state = SUSPENDED; in fsl_edma_suspend_late()
831 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_suspend_late()
841 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_resume_early()
844 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_resume_early()
845 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_resume_early()
846 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_resume_early()
848 fsl_chan->pm_state = RUNNING; in fsl_edma_resume_early()
850 if (fsl_chan->srcid != 0) in fsl_edma_resume_early()
851 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true); in fsl_edma_resume_early()
854 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) in fsl_edma_resume_early()
855 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_resume_early()
861 * eDMA provides the service to others, so it should be suspend late
862 * and resume early. When eDMA suspend, all of the clients should stop
872 .name = "fsl-edma",
892 MODULE_ALIAS("platform:fsl-edma");
893 MODULE_DESCRIPTION("Freescale eDMA engine driver");