1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2013,2018,2020-2021 Intel Corporation
38 	struct device *slave = dwc->chan.slave;  in idma32_get_slave_devfn()
43 	return to_pci_dev(slave)->devfn;  in idma32_get_slave_devfn()
48 	struct dw_dma *dw = to_dw_dma(dwc->chan.device);  in idma32_initialize_chan_xbar()
58 	value |= dwc->chan.chan_id;  in idma32_initialize_chan_xbar()
63 	value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id));  in idma32_initialize_chan_xbar()
69 	switch (dwc->direction) {  in idma32_initialize_chan_xbar()
80 		 * Memory-to-Memory and Device-to-Device are ignored for now.  in idma32_initialize_chan_xbar()
82 		 * For Memory-to-Memory transfers we would need to set mode  in idma32_initialize_chan_xbar()
88 	writel(value, misc + DMA_CTL_CH(dwc->chan.chan_id));  in idma32_initialize_chan_xbar()
91 	value = readl(misc + DMA_XBAR_SEL(dwc->chan.chan_id));  in idma32_initialize_chan_xbar()
97 	switch (dwc->direction) {  in idma32_initialize_chan_xbar()
105 		/* Memory-to-Memory and Device-to-Device are ignored for now */  in idma32_initialize_chan_xbar()
109 	writel(value, misc + DMA_XBAR_SEL(dwc->chan.chan_id));  in idma32_initialize_chan_xbar()
112 	switch (dwc->direction) {  in idma32_initialize_chan_xbar()
114 		dst_id = dwc->chan.chan_id;  in idma32_initialize_chan_xbar()
115 		src_id = dwc->dws.src_id;  in idma32_initialize_chan_xbar()
118 		dst_id = dwc->dws.dst_id;  in idma32_initialize_chan_xbar()
119 		src_id = dwc->chan.chan_id;  in idma32_initialize_chan_xbar()
122 		/* Memory-to-Memory and Device-to-Device are ignored for now */  in idma32_initialize_chan_xbar()
133 	/* Request line extension (2 bits) */  in idma32_initialize_chan_xbar()
150 	cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);  in idma32_initialize_chan_generic()
151 	cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);  in idma32_initialize_chan_generic()
153 	/* Request line extension (2 bits) */  in idma32_initialize_chan_generic()
154 	cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);  in idma32_initialize_chan_generic()
155 	cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);  in idma32_initialize_chan_generic()
186 	if (bytes > dwc->block_size) {  in idma32_bytes2block()
187 		block = dwc->block_size;  in idma32_bytes2block()
188 		*len = dwc->block_size;  in idma32_bytes2block()
204 	return maxburst > 1 ? fls(maxburst) - 1 : 0;  in idma32_encode_maxburst()
209 	struct dma_slave_config	*sconfig = &dwc->dma_sconfig;  in idma32_prepare_ctllo()
212 	if (dwc->direction == DMA_MEM_TO_DEV)  in idma32_prepare_ctllo()
213 		dmsize = idma32_encode_maxburst(sconfig->dst_maxburst);  in idma32_prepare_ctllo()
214 	else if (dwc->direction == DMA_DEV_TO_MEM)  in idma32_prepare_ctllo()
215 		smsize = idma32_encode_maxburst(sconfig->src_maxburst);  in idma32_prepare_ctllo()
223 	snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id);  in idma32_set_device_name()
230  * slice FIFO on equal parts between channels.
244 	/* Program FIFO Partition registers - 64 bytes per channel */  in idma32_fifo_partition()
265 	dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);  in idma32_dma_probe()
267 		return -ENOMEM;  in idma32_dma_probe()
270 	if (chip->pdata->quirks & DW_DMA_QUIRK_XBAR_PRESENT)  in idma32_dma_probe()
271 		dw->initialize_chan = idma32_initialize_chan_xbar;  in idma32_dma_probe()
273 		dw->initialize_chan = idma32_initialize_chan_generic;  in idma32_dma_probe()
274 	dw->suspend_chan = idma32_suspend_chan;  in idma32_dma_probe()
275 	dw->resume_chan = idma32_resume_chan;  in idma32_dma_probe()
276 	dw->prepare_ctllo = idma32_prepare_ctllo;  in idma32_dma_probe()
277 	dw->bytes2block = idma32_bytes2block;  in idma32_dma_probe()
278 	dw->block2bytes = idma32_block2bytes;  in idma32_dma_probe()
281 	dw->set_device_name = idma32_set_device_name;  in idma32_dma_probe()
282 	dw->disable = idma32_disable;  in idma32_dma_probe()
283 	dw->enable = idma32_enable;  in idma32_dma_probe()
285 	chip->dw = dw;  in idma32_dma_probe()