1 /* SPDX-License-Identifier: GPL-2.0-only */
22  * (port-driver, region-driver, nvdimm object-drivers... etc).
86 		return -EINVAL;  in eig_to_granularity()
91 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
99 		*ways = 3 << (eiw - 8);  in eiw_to_ways()
102 		return -EINVAL;  in eiw_to_ways()
112 		return -EINVAL;  in granularity_to_eig()
113 	*eig = ilog2(granularity) - 8;  in granularity_to_eig()
120 		return -EINVAL;  in ways_to_eiw()
126 		return -EINVAL;  in ways_to_eiw()
129 		return -EINVAL;  in ways_to_eiw()
178 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
204  * Using struct_group() allows for per register-block-type helper routines,
205  * without requiring block-type agnostic code to include the prefix.
232 	 * RCH downstream port specific RAS register
233 	 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
240 	 * RCD upstream port specific PCIe cap register
241 	 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB
271  * struct cxl_register_map - DVSEC harvested register block mapping parameters
273  * @base: virtual base of the register-block-BAR + @block_offset
275  * @max_size: maximum mapping size to perform register search
317 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
346 #define CXL_QOS_CLASS_INVALID -1
349  * struct cxl_decoder - Common CXL HDM Decoder Attributes
358  * @commit: device/decoder-type specific callback to commit settings to hw
359  * @reset: device/decoder-type specific callback to reset hw settings
386 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode)  in cxl_decoder_mode_name()  argument
395 	if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED)  in cxl_decoder_mode_name()
396 		return names[mode];  in cxl_decoder_mode_name()
410  * struct cxl_endpoint_decoder - Endpoint  / SPA to DPA decoder
414  * @mode: which memory type / access-mode-partition this decoder targets
422 	enum cxl_decoder_mode mode;  member
428  * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
435  * come in two flavors, root-level decoders, statically defined by platform
436  * firmware, and mid-level decoders, where interleave-granularity,
437  * interleave-width, and the target list are mutable.
449  * struct cxl_root_decoder - Static platform CXL address decoder
452  * @hpa_to_spa: translate CXL host-physical-address to Platform system-physical-address
469  * enum cxl_config_state - State machine for region configuration
476  * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
487  * struct cxl_region_params - region settings
524  * struct cxl_region - CXL region
527  * @mode: Endpoint decoder allocation / access mode
540 	enum cxl_decoder_mode mode;  member
554 	struct cxl_port *port;  member
581 	struct cxl_pmem_region_mapping mapping[];  member
591  * struct cxl_port - logical collection of upstream port devices and
592  *		     downstream port devices to construct a CXL memory
594  * @dev: this port's device
595  * @uport_dev: PCI or platform device implementing the upstream port capability
596  * @host_bridge: Shortcut to the platform attach point for this port
597  * @id: id for port device-name
599  * @endpoints: cxl_ep instances, endpoints that are a descendant of this port
600  * @regions: cxl_region_ref instances, regions mapped by this port
601  * @parent_dport: dport that points to this port in the parent
603  * @reg_map: component and ras register mapping parameters
607  * @dead: last ep has been removed, force port re-creation
608  * @depth: How deep this port is relative to the root. depth 0 is the root.
638  * struct cxl_root - logical collection of root cxl_port items
640  * @port: cxl_port member
644 	struct cxl_port port;  member
649 to_cxl_root(const struct cxl_port *port)  in to_cxl_root()  argument
651 	return container_of(port, struct cxl_root, port);  in to_cxl_root()
661 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)  in cxl_find_dport_by_dev()  argument
663 	return xa_load(&port->dports, (unsigned long)dport_dev);  in cxl_find_dport_by_dev()
672  * struct cxl_dport - CXL downstream port
674  * @reg_map: component and ras register mapping parameters
677  * @rch: Indicate whether this dport was enumerated in RCH or VH mode
678  * @port: reference to cxl_port that contains this downstream port
689 	struct cxl_port *port;  member
696  * struct cxl_ep - track an endpoint's interest in a port
698  * @dport: which dport routes to this endpoint on @port
699  * @next: cxl switch port across the link attached to @dport NULL if
709  * struct cxl_region_ref - track a region's interest in a port
710  * @port: point in topology to install this reference
711  * @decoder: decoder assigned for @region in @port
713  * @endpoints: cxl_ep references for region members beneath @port
715  * @nr_eps: number of endpoints beneath @port
719 	struct cxl_port *port;  member
730  * CXL port topology. All other CXL ports have another CXL port as their
731  * parent and their ->uport_dev / host device is out-of-line of the port
734 static inline bool is_cxl_root(struct cxl_port *port)  in is_cxl_root()  argument
736 	return port->uport_dev == port->dev.parent;  in is_cxl_root()
739 int cxl_num_decoders_committed(struct cxl_port *port);
746 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
753 struct cxl_root *find_cxl_root(struct cxl_port *port);
757 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev))
767 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
770 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
789 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
791 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
794 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
800 	return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld);  in cxl_root_decoder_autoremove()
805  * struct cxl_endpoint_dvsec_info - Cached DVSEC info
808  * @port: endpoint port associated with this info instance
814 	struct cxl_port *port;  member
819 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
823 int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
824 int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
864 						     struct cxl_port *port);
869 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port);
897 void cxl_endpoint_parse_cdat(struct cxl_port *port);
898 void cxl_switch_parse_cdat(struct cxl_port *port);
900 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
912 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port);