Lines Matching +full:offset +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/io-64-nonatomic-lo-hi.h>
17 * Vendor-specific) and / or descriptors provided by platform firmware.
28 * cxl_probe_component_regs() - Detect CXL Component register blocks
47 * CXL.cache and CXL.mem registers are at offset 0x1000 as defined in in cxl_probe_component_regs()
66 u16 cap_id, offset; in cxl_probe_component_regs() local
72 offset = FIELD_GET(CXL_CM_CAP_PTR_MASK, hdr); in cxl_probe_component_regs()
73 register_block = base + offset; in cxl_probe_component_regs()
81 dev_dbg(dev, "found HDM decoder capability (0x%x)\n", in cxl_probe_component_regs()
82 offset); in cxl_probe_component_regs()
86 rmap = &map->hdm_decoder; in cxl_probe_component_regs()
90 dev_dbg(dev, "found RAS capability (0x%x)\n", in cxl_probe_component_regs()
91 offset); in cxl_probe_component_regs()
93 rmap = &map->ras; in cxl_probe_component_regs()
96 dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id, in cxl_probe_component_regs()
97 offset); in cxl_probe_component_regs()
103 rmap->valid = true; in cxl_probe_component_regs()
104 rmap->id = cap_id; in cxl_probe_component_regs()
105 rmap->offset = CXL_CM_OFFSET + offset; in cxl_probe_component_regs()
106 rmap->size = length; in cxl_probe_component_regs()
112 * cxl_probe_device_regs() - Detect CXL Device register blocks
136 u32 offset, length; in cxl_probe_device_regs() local
141 offset = readl(base + cap * 0x10 + 0x4); in cxl_probe_device_regs()
147 dev_dbg(dev, "found Status capability (0x%x)\n", offset); in cxl_probe_device_regs()
148 rmap = &map->status; in cxl_probe_device_regs()
151 dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset); in cxl_probe_device_regs()
152 rmap = &map->mbox; in cxl_probe_device_regs()
155 dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset); in cxl_probe_device_regs()
158 dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset); in cxl_probe_device_regs()
159 rmap = &map->memdev; in cxl_probe_device_regs()
163 dev_dbg(dev, "Vendor cap ID: %#x offset: %#x\n", cap_id, offset); in cxl_probe_device_regs()
165 dev_dbg(dev, "Unknown cap ID: %#x offset: %#x\n", cap_id, offset); in cxl_probe_device_regs()
171 rmap->valid = true; in cxl_probe_device_regs()
172 rmap->id = cap_id; in cxl_probe_device_regs()
173 rmap->offset = offset; in cxl_probe_device_regs()
174 rmap->size = length; in cxl_probe_device_regs()
190 resource_size_t end = addr + length - 1; in devm_cxl_iomap_block()
192 dev_err(dev, "Failed to request region %pa-%pa\n", &addr, &end); in devm_cxl_iomap_block()
207 struct device *host = map->host; in cxl_map_component_regs()
212 { &map->component_map.hdm_decoder, ®s->hdm_decoder }, in cxl_map_component_regs()
213 { &map->component_map.ras, ®s->ras }, in cxl_map_component_regs()
222 if (!mi->rmap->valid) in cxl_map_component_regs()
224 if (!test_bit(mi->rmap->id, &map_mask)) in cxl_map_component_regs()
226 addr = map->resource + mi->rmap->offset; in cxl_map_component_regs()
227 length = mi->rmap->size; in cxl_map_component_regs()
228 *(mi->addr) = devm_cxl_iomap_block(host, addr, length); in cxl_map_component_regs()
229 if (!*(mi->addr)) in cxl_map_component_regs()
230 return -ENOMEM; in cxl_map_component_regs()
240 struct device *host = map->host; in cxl_map_device_regs()
241 resource_size_t phys_addr = map->resource; in cxl_map_device_regs()
246 { &map->device_map.status, ®s->status, }, in cxl_map_device_regs()
247 { &map->device_map.mbox, ®s->mbox, }, in cxl_map_device_regs()
248 { &map->device_map.memdev, ®s->memdev, }, in cxl_map_device_regs()
257 if (!mi->rmap->valid) in cxl_map_device_regs()
260 addr = phys_addr + mi->rmap->offset; in cxl_map_device_regs()
261 length = mi->rmap->size; in cxl_map_device_regs()
262 *(mi->addr) = devm_cxl_iomap_block(host, addr, length); in cxl_map_device_regs()
263 if (!*(mi->addr)) in cxl_map_device_regs()
264 return -ENOMEM; in cxl_map_device_regs()
276 u64 offset = ((u64)reg_hi << 32) | in cxl_decode_regblock() local
279 if (offset > pci_resource_len(pdev, bar)) { in cxl_decode_regblock()
280 dev_warn(&pdev->dev, in cxl_decode_regblock()
281 "BAR%d: %pr: too small (offset: %pa, type: %d)\n", bar, in cxl_decode_regblock()
282 &pdev->resource[bar], &offset, reg_type); in cxl_decode_regblock()
286 map->reg_type = reg_type; in cxl_decode_regblock()
287 map->resource = pci_resource_start(pdev, bar) + offset; in cxl_decode_regblock()
288 map->max_size = pci_resource_len(pdev, bar) - offset; in cxl_decode_regblock()
293 * __cxl_find_regblock_instance() - Locate a register block or count instances by type / index
297 * 0 - if register block enumerated.
298 * >= 0 - if counting instances.
299 * < 0 - error code otherwise.
309 .host = &pdev->dev, in __cxl_find_regblock_instance()
316 return -ENXIO; in __cxl_find_regblock_instance()
322 regblocks = (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8; in __cxl_find_regblock_instance()
333 if (map->reg_type == type) { in __cxl_find_regblock_instance()
340 map->resource = CXL_RESOURCE_NONE; in __cxl_find_regblock_instance()
344 return -ENODEV; in __cxl_find_regblock_instance()
348 * cxl_find_regblock_instance() - Locate a register block by type / index
368 * cxl_find_regblock() - Locate register blocks by type
386 * cxl_count_regblock() - Count instances of a given regblock type.
392 * Return: non-negative count of matching regblocks, negative error code otherwise.
404 struct device *dev = map->host; in cxl_map_pmu_regs()
407 phys_addr = map->resource; in cxl_map_pmu_regs()
408 regs->pmu = devm_cxl_iomap_block(dev, phys_addr, CXL_PMU_REGMAP_SIZE); in cxl_map_pmu_regs()
409 if (!regs->pmu) in cxl_map_pmu_regs()
410 return -ENOMEM; in cxl_map_pmu_regs()
418 struct device *host = map->host; in cxl_map_regblock()
420 map->base = ioremap(map->resource, map->max_size); in cxl_map_regblock()
421 if (!map->base) { in cxl_map_regblock()
423 return -ENOMEM; in cxl_map_regblock()
426 dev_dbg(host, "Mapped CXL Memory Device resource %pa\n", &map->resource); in cxl_map_regblock()
432 iounmap(map->base); in cxl_unmap_regblock()
433 map->base = NULL; in cxl_unmap_regblock()
440 struct device *host = map->host; in cxl_probe_regs()
441 void __iomem *base = map->base; in cxl_probe_regs()
443 switch (map->reg_type) { in cxl_probe_regs()
445 comp_map = &map->component_map; in cxl_probe_regs()
450 dev_map = &map->device_map; in cxl_probe_regs()
452 if (!dev_map->status.valid || !dev_map->mbox.valid || in cxl_probe_regs()
453 !dev_map->memdev.valid) { in cxl_probe_regs()
455 !dev_map->status.valid ? "status " : "", in cxl_probe_regs()
456 !dev_map->mbox.valid ? "mbox " : "", in cxl_probe_regs()
457 !dev_map->memdev.valid ? "memdev " : ""); in cxl_probe_regs()
458 return -ENXIO; in cxl_probe_regs()
488 u16 offset = 0; in cxl_rcrb_to_aer() local
501 cap_hdr = readl(addr + offset); in cxl_rcrb_to_aer()
503 offset = PCI_EXT_CAP_NEXT(cap_hdr); in cxl_rcrb_to_aer()
505 /* Offset 0 terminates capability list. */ in cxl_rcrb_to_aer()
506 if (!offset) in cxl_rcrb_to_aer()
508 cap_hdr = readl(addr + offset); in cxl_rcrb_to_aer()
511 if (offset) in cxl_rcrb_to_aer()
512 dev_dbg(dev, "found AER extended capability (0x%x)\n", offset); in cxl_rcrb_to_aer()
518 return offset; in cxl_rcrb_to_aer()
523 resource_size_t rcrb = dport->rcrb.base; in cxl_rcrb_to_linkcap()
526 u16 offset; in cxl_rcrb_to_linkcap() local
538 offset = FIELD_GET(PCI_RCRB_CAP_LIST_ID_MASK, readw(addr + PCI_CAPABILITY_LIST)); in cxl_rcrb_to_linkcap()
539 cap_hdr = readl(addr + offset); in cxl_rcrb_to_linkcap()
541 offset = FIELD_GET(PCI_RCRB_CAP_HDR_NEXT_MASK, cap_hdr); in cxl_rcrb_to_linkcap()
542 if (offset == 0 || offset > SZ_4K) { in cxl_rcrb_to_linkcap()
543 offset = 0; in cxl_rcrb_to_linkcap()
546 cap_hdr = readl(addr + offset); in cxl_rcrb_to_linkcap()
551 if (!offset) in cxl_rcrb_to_linkcap()
554 return offset; in cxl_rcrb_to_linkcap()
563 ri = &dport->rcrb; in cxl_dport_map_rcd_linkcap()
564 pos = cxl_rcrb_to_linkcap(&pdev->dev, dport); in cxl_dport_map_rcd_linkcap()
566 return -ENXIO; in cxl_dport_map_rcd_linkcap()
568 dport_pcie_cap = devm_cxl_iomap_block(&pdev->dev, in cxl_dport_map_rcd_linkcap()
569 ri->base + pos, in cxl_dport_map_rcd_linkcap()
571 dport->regs.rcd_pcie_cap = dport_pcie_cap; in cxl_dport_map_rcd_linkcap()
581 resource_size_t rcrb = ri->base; in __rcrb_to_component()
613 * Sanity check, see CXL 3.0 Figure 9-8 CXL Device that Does Not in __rcrb_to_component()
644 if (!dport->rch) in cxl_rcd_component_reg_phys()
646 return __rcrb_to_component(dev, &dport->rcrb, CXL_RCRB_UPSTREAM); in cxl_rcd_component_reg_phys()