28  * 1. Interleave granularity
29  * 2. Interleave size
488 	 * Even for x3, x6, and x12 interleaves the region interleave must be a  in interleave_ways_store()
489 	 * power of 2 multiple of the host bridge interleave.  in interleave_ways_store()
493 		dev_dbg(&cxlr->dev, "invalid interleave: %d\n", val);  in interleave_ways_store()
557 	 * interleave result in needing multiple endpoints to support a single  in interleave_granularity_store()
558 	 * slot in the interleave (possible to support in the future). Regions  in interleave_granularity_store()
559 	 * with a granularity greater than the root interleave result in invalid  in interleave_granularity_store()
1035  * @pos: interleave position of @cxled in @cxlr
1259 	 *   interleave bits are none.  in check_interleave_cap()
1266 	 *   interleave bits are none.  in check_interleave_cap()
1371 		dev_dbg(&cxlr->dev, "%s:%s: invalid parent interleave: %d\n",  in cxl_port_setup_targets()
1380 		dev_dbg(&cxlr->dev, "%s:%s: invalid port interleave: %d\n",  in cxl_port_setup_targets()
1386 	 * Interleave granularity is a multiple of @parent_port granularity.  in cxl_port_setup_targets()
1387 	 * Multiplier is the parent port interleave ways.  in cxl_port_setup_targets()
1399 		dev_dbg(&cxlr->dev, "%s:%s: invalid interleave: %d\n",  in cxl_port_setup_targets()
1800 	 * Example: the expected interleave order of the 4-way region shown  in cxl_calc_interleave_pos()
1865 	/* Keep the cxlr target list in interleave position order */  in cxl_region_sort_targets()
1903 	/* all full of members, or interleave config not established? */  in cxl_region_attach()
1908 		dev_dbg(&cxlr->dev, "interleave config missing\n");  in cxl_region_attach()
2031 	 * A fail message here means that this interleave config  in cxl_region_attach()
2890 	 * The device position in the region interleave set was removed  in cxl_dpa_to_hpa()
2894 	 * The placement of 'pos' in the HPA is determined by interleave  in cxl_dpa_to_hpa()