Lines Matching +full:system +full:- +full:cache +full:- +full:controller

1 # SPDX-License-Identifier: GPL-2.0-only
13 	  layers three protocols on that signalling (CXL.io, CXL.cache, and
14 	  CXL.mem). The CXL.cache protocol allows devices to hold cachelines
26 	  The CXL specification defines a "CXL memory device" sub-class in the
27 	  PCI "memory controller" base class of devices. Device's identified by
29 	  memory to be mapped into the system address map (Host-managed Device
70 	  (https://www.computeexpresslink.org/spec-landing). The CXL core
72 	  hierarchy to map regions that represent System RAM, or Persistent
84 	  managed via a bridge driver from CXL to the LIBNVDIMM system
95 	  The CXL.mem protocol allows a device to act as a provider of "System
97 	  memory were attached to the typical CPU memory controller. This is
98 	  known as HDM "Host-managed Device Memory".
143 	  Documentation/ABI/testing/sysfs-edac-scrub.
161 	  Documentation/ABI/testing/sysfs-edac-ecs.
182 	  Documentation/ABI/testing/sysfs-edac-memory-repair.
206 	  system-physical address range. For CXL regions established by
207 	  platform-firmware this option enables memory error handling to
209 	  range. Otherwise, platform-firmware managed CXL is enabled by being
210 	  placed in the system address map and does not need a driver.
215 	bool "CXL: Region Cache Management Bypass (TEST)"
222 	  fails the region will fail to enable.  Reasons for cache
223 	  invalidation failure are due to the CPU not providing a cache
227 	  regions when there might be conflicting contents in the CPU cache.