Lines Matching +full:memory +full:- +full:to +full:- +full:memory
1 # SPDX-License-Identifier: GPL-2.0-only
13 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
14 locally, the CXL.mem protocol allows devices to be fully coherent
15 memory targets, the CXL.io protocol is equivalent to PCI Express.
16 Say 'y' to enable support for the configuration and management of
25 The CXL specification defines a "CXL memory device" sub-class in the
26 PCI "memory controller" base class of devices. Device's identified by
28 memory to be mapped into the system address map (Host-managed Device
29 Memory (HDM)).
31 Say 'y/m' to enable a driver that will attach to CXL memory expander
32 devices enumerated by the memory device class code for configuration
39 bool "RAW Command Interface for Memory Devices"
50 the driver it is useful to be able to submit any possible command to
51 the hardware, even commands that may crash the kernel due to their
52 potential impact to memory currently in use by the kernel.
65 Enable support for host managed device memory (HDM) resources
66 published by a platform's ACPI CXL memory layout description. See
68 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
69 (https://www.computeexpresslink.org/spec-landing). The CXL core
70 consumes these resource to publish the root of a cxl_port decode
71 hierarchy to map regions that represent System RAM, or Persistent
72 Memory regions to be managed by LIBNVDIMM.
77 tristate "CXL PMEM: Persistent Memory Support"
81 In addition to typical memory resources a platform may also advertise
82 support for persistent memory attached via CXL. This support is
83 managed via a bridge driver from CXL to the LIBNVDIMM system
84 subsystem. Say 'y/m' to enable support for enumerating and
85 provisioning the persistent memory capacity of CXL memory expanders.
90 tristate "CXL: Memory Expansion"
94 The CXL.mem protocol allows a device to act as a provider of "System
95 RAM" and/or "Persistent Memory" that is fully coherent as if the
96 memory were attached to the typical CPU memory controller. This is
97 known as HDM "Host-managed Device Memory".
99 Say 'y/m' to enable a driver that will attach to CXL.mem devices for
100 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
121 Enable the CXL core to enumerate and provision CXL regions. A CXL
123 system-physical address range. For CXL regions established by
124 platform-firmware this option enables memory error handling to
125 identify the devices participating in a given interleaved memory
126 range. Otherwise, platform-firmware managed CXL is enabled by being
136 the content of CPU caches without notifying those caches to
138 to invalidate caches when those events occur. If that invalidation
139 fails the region will fail to enable. Reasons for cache
140 invalidation failure are due to the CPU not providing a cache
141 invalidation mechanism. For example usage of wbinvd is restricted to