Lines Matching +full:memory +full:- +full:to +full:- +full:memory
1 # SPDX-License-Identifier: GPL-2.0-only
14 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
15 locally, the CXL.mem protocol allows devices to be fully coherent
16 memory targets, the CXL.io protocol is equivalent to PCI Express.
17 Say 'y' to enable support for the configuration and management of
26 The CXL specification defines a "CXL memory device" sub-class in the
27 PCI "memory controller" base class of devices. Device's identified by
29 memory to be mapped into the system address map (Host-managed Device
30 Memory (HDM)).
32 Say 'y/m' to enable a driver that will attach to CXL memory expander
33 devices enumerated by the memory device class code for configuration
40 bool "RAW Command Interface for Memory Devices"
51 the driver it is useful to be able to submit any possible command to
52 the hardware, even commands that may crash the kernel due to their
53 potential impact to memory currently in use by the kernel.
66 Enable support for host managed device memory (HDM) resources
67 published by a platform's ACPI CXL memory layout description. See
69 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
70 (https://www.computeexpresslink.org/spec-landing). The CXL core
71 consumes these resource to publish the root of a cxl_port decode
72 hierarchy to map regions that represent System RAM, or Persistent
73 Memory regions to be managed by LIBNVDIMM.
78 tristate "CXL PMEM: Persistent Memory Support"
82 In addition to typical memory resources a platform may also advertise
83 support for persistent memory attached via CXL. This support is
84 managed via a bridge driver from CXL to the LIBNVDIMM system
85 subsystem. Say 'y/m' to enable support for enumerating and
86 provisioning the persistent memory capacity of CXL memory expanders.
91 tristate "CXL: Memory Expansion"
95 The CXL.mem protocol allows a device to act as a provider of "System
96 RAM" and/or "Persistent Memory" that is fully coherent as if the
97 memory were attached to the typical CPU memory controller. This is
98 known as HDM "Host-managed Device Memory".
100 Say 'y/m' to enable a driver that will attach to CXL.mem devices for
101 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
112 optionally defined features such as memory sparing or post package
118 bool "CXL: EDAC Memory Features"
124 The CXL EDAC memory feature is optional and allows host to
125 control the EDAC memory features configurations of CXL memory
128 Say 'y' if you have an expert need to change default settings
129 of a memory RAS feature established by the platform/device.
137 The CXL EDAC scrub control is optional and allows host to
138 control the scrub feature configurations of CXL memory expander
142 published with memory scrub control attributes as described by
143 Documentation/ABI/testing/sysfs-edac-scrub.
145 Say 'y' if you have an expert need to change default settings
146 of a memory scrub feature established by the platform/device
155 The CXL EDAC ECS control is optional and allows host to
156 control the ECS feature configurations of CXL memory expander
159 When enabled 'cxl_mem' EDAC devices are published with memory
161 Documentation/ABI/testing/sysfs-edac-ecs.
163 Say 'y' if you have an expert need to change default settings
164 of a memory ECS feature established by the platform/device.
168 bool "Enable CXL Memory Repair"
172 The CXL EDAC memory repair control is optional and allows host
173 to control the memory repair features (e.g. sparing, PPR)
174 configurations of CXL memory expander devices.
176 When enabled, the memory repair feature requires an additional
177 memory of approximately 43KB to store CXL DRAM and CXL general
180 When enabled 'cxl_mem' EDAC devices are published with memory
182 Documentation/ABI/testing/sysfs-edac-memory-repair.
184 Say 'y' if you have an expert need to change default settings
185 of a memory repair feature established by the platform/device.
204 Enable the CXL core to enumerate and provision CXL regions. A CXL
206 system-physical address range. For CXL regions established by
207 platform-firmware this option enables memory error handling to
208 identify the devices participating in a given interleaved memory
209 range. Otherwise, platform-firmware managed CXL is enabled by being
219 the content of CPU caches without notifying those caches to
221 to invalidate caches when those events occur. If that invalidation
222 fails the region will fail to enable. Reasons for cache
223 invalidation failure are due to the CPU not providing a cache
224 invalidation mechanism. For example usage of wbinvd is restricted to