Lines Matching +full:in +full:- +full:memory
1 # SPDX-License-Identifier: GPL-2.0-only
16 memory targets, the CXL.io protocol is equivalent to PCI Express.
26 The CXL specification defines a "CXL memory device" sub-class in the
27 PCI "memory controller" base class of devices. Device's identified by
29 memory to be mapped into the system address map (Host-managed Device
30 Memory (HDM)).
32 Say 'y/m' to enable a driver that will attach to CXL memory expander
33 devices enumerated by the memory device class code for configuration
35 Type 3 CXL Device in the CXL 2.0 specification for more details.
40 bool "RAW Command Interface for Memory Devices"
46 number for each specification defined opcode. At any given point in
53 potential impact to memory currently in use by the kernel.
66 Enable support for host managed device memory (HDM) resources
67 published by a platform's ACPI CXL memory layout description. See
68 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
69 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
70 (https://www.computeexpresslink.org/spec-landing). The CXL core
73 Memory regions to be managed by LIBNVDIMM.
78 tristate "CXL PMEM: Persistent Memory Support"
82 In addition to typical memory resources a platform may also advertise
83 support for persistent memory attached via CXL. This support is
86 provisioning the persistent memory capacity of CXL memory expanders.
91 tristate "CXL: Memory Expansion"
96 RAM" and/or "Persistent Memory" that is fully coherent as if the
97 memory were attached to the typical CPU memory controller. This is
98 known as HDM "Host-managed Device Memory".
101 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
112 optionally defined features such as memory sparing or post package
118 bool "CXL: EDAC Memory Features"
124 The CXL EDAC memory feature is optional and allows host to
125 control the EDAC memory features configurations of CXL memory
129 of a memory RAS feature established by the platform/device.
138 control the scrub feature configurations of CXL memory expander
142 published with memory scrub control attributes as described by
143 Documentation/ABI/testing/sysfs-edac-scrub.
146 of a memory scrub feature established by the platform/device
156 control the ECS feature configurations of CXL memory expander
159 When enabled 'cxl_mem' EDAC devices are published with memory
161 Documentation/ABI/testing/sysfs-edac-ecs.
164 of a memory ECS feature established by the platform/device.
168 bool "Enable CXL Memory Repair"
172 The CXL EDAC memory repair control is optional and allows host
173 to control the memory repair features (e.g. sparing, PPR)
174 configurations of CXL memory expander devices.
176 When enabled, the memory repair feature requires an additional
177 memory of approximately 43KB to store CXL DRAM and CXL general
180 When enabled 'cxl_mem' EDAC devices are published with memory
182 Documentation/ABI/testing/sysfs-edac-memory-repair.
185 of a memory repair feature established by the platform/device.
206 system-physical address range. For CXL regions established by
207 platform-firmware this option enables memory error handling to
208 identify the devices participating in a given interleaved memory
209 range. Otherwise, platform-firmware managed CXL is enabled by being
210 placed in the system address map and does not need a driver.
227 regions when there might be conflicting contents in the CPU cache.