Lines Matching full:memory
15 memory targets, the CXL.io protocol is equivalent to PCI Express.
25 The CXL specification defines a "CXL memory device" sub-class in the
26 PCI "memory controller" base class of devices. Device's identified by
28 memory to be mapped into the system address map (Host-managed Device
29 Memory (HDM)).
31 Say 'y/m' to enable a driver that will attach to CXL memory expander
32 devices enumerated by the memory device class code for configuration
39 bool "RAW Command Interface for Memory Devices"
52 potential impact to memory currently in use by the kernel.
65 Enable support for host managed device memory (HDM) resources
66 published by a platform's ACPI CXL memory layout description. See
68 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
72 Memory regions to be managed by LIBNVDIMM.
77 tristate "CXL PMEM: Persistent Memory Support"
81 In addition to typical memory resources a platform may also advertise
82 support for persistent memory attached via CXL. This support is
85 provisioning the persistent memory capacity of CXL memory expanders.
90 tristate "CXL: Memory Expansion"
95 RAM" and/or "Persistent Memory" that is fully coherent as if the
96 memory were attached to the typical CPU memory controller. This is
97 known as HDM "Host-managed Device Memory".
100 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
124 platform-firmware this option enables memory error handling to
125 identify the devices participating in a given interleaved memory