Lines Matching +full:0 +full:x2000
20 #define EIP197_HIA_VERSION_BE 0xca35
21 #define EIP197_HIA_VERSION_LE 0x35ca
22 #define EIP97_VERSION_LE 0x9e61
23 #define EIP196_VERSION_LE 0x3bc4
24 #define EIP197_VERSION_LE 0x3ac5
25 #define EIP96_VERSION_LE 0x9f60
26 #define EIP201_VERSION_LE 0x36c9
27 #define EIP206_VERSION_LE 0x31ce
28 #define EIP207_VERSION_LE 0x30cf
29 #define EIP197_REG_LO16(reg) (reg & 0xffff)
30 #define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff)
31 #define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff)
32 #define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \
33 ((reg >> 4) & 0xf0) | \
34 ((reg >> 12) & 0xf))
70 #define EIP197_XLX_GPIO_BASE 0x200000
71 #define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
72 #define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2
73 #define EIP197_XLX_USER_INT_ENB_MSK 0x2004
74 #define EIP197_XLX_USER_INT_ENB_SET 0x2008
75 #define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c
76 #define EIP197_XLX_USER_INT_BLOCK 0x2040
77 #define EIP197_XLX_USER_INT_PEND 0x2048
78 #define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080
79 #define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100
80 #define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084
81 #define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504
82 #define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088
83 #define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908
84 #define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c
85 #define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c
104 #define EIP197_HIA_AIC_BASE 0x90000
105 #define EIP197_HIA_AIC_G_BASE 0x90000
106 #define EIP197_HIA_AIC_R_BASE 0x90800
107 #define EIP197_HIA_AIC_xDR_BASE 0x80000
108 #define EIP197_HIA_DFE_BASE 0x8c000
109 #define EIP197_HIA_DFE_THR_BASE 0x8c040
110 #define EIP197_HIA_DSE_BASE 0x8d000
111 #define EIP197_HIA_DSE_THR_BASE 0x8d040
112 #define EIP197_HIA_GEN_CFG_BASE 0xf0000
113 #define EIP197_PE_BASE 0xa0000
114 #define EIP197_GLOBAL_BASE 0xf0000
117 #define EIP97_HIA_AIC_BASE 0x0
118 #define EIP97_HIA_AIC_G_BASE 0x0
119 #define EIP97_HIA_AIC_R_BASE 0x0
120 #define EIP97_HIA_AIC_xDR_BASE 0x0
121 #define EIP97_HIA_DFE_BASE 0xf000
122 #define EIP97_HIA_DFE_THR_BASE 0xf200
123 #define EIP97_HIA_DSE_BASE 0xf400
124 #define EIP97_HIA_DSE_THR_BASE 0xf600
125 #define EIP97_HIA_GEN_CFG_BASE 0x10000
126 #define EIP97_PE_BASE 0x10000
127 #define EIP97_GLOBAL_BASE 0x10000
130 #define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
132 #define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800)
133 #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000
134 #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004
135 #define EIP197_HIA_xDR_RING_SIZE 0x0018
136 #define EIP197_HIA_xDR_DESC_SIZE 0x001c
137 #define EIP197_HIA_xDR_CFG 0x0020
138 #define EIP197_HIA_xDR_DMA_CFG 0x0024
139 #define EIP197_HIA_xDR_THRESH 0x0028
140 #define EIP197_HIA_xDR_PREP_COUNT 0x002c
141 #define EIP197_HIA_xDR_PROC_COUNT 0x0030
142 #define EIP197_HIA_xDR_PREP_PNTR 0x0034
143 #define EIP197_HIA_xDR_PROC_PNTR 0x0038
144 #define EIP197_HIA_xDR_STAT 0x003c
147 #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
148 #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
149 #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
150 #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
151 #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
152 #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
153 #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
154 #define EIP197_HIA_RA_PE_STAT 0x0014
155 #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
156 #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
157 #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
158 #define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
159 #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r))
160 #define EIP197_HIA_AIC_R_VERSION(r) (0xe01c - EIP197_HIA_AIC_R_OFF(r))
161 #define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808
162 #define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810
163 #define EIP197_HIA_AIC_G_ACK 0xf810
164 #define EIP197_HIA_MST_CTRL 0xfff4
165 #define EIP197_HIA_OPTIONS 0xfff8
166 #define EIP197_HIA_VERSION 0xfffc
167 #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
168 #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
169 #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
170 #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
171 #define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
172 #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
173 #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
174 #define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
175 #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
176 #define EIP197_PE_ICE_VERSION(n) (0x0ffc + (0x2000 * (n)))
177 #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n)))
178 #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
179 #define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
180 #define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
181 #define EIP197_PE_EIP96_TOKEN_CTRL2(n) (0x102c + (0x2000 * (n)))
182 #define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n)))
183 #define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n)))
184 #define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n)))
185 #define EIP197_PE_OCE_VERSION(n) (0x1bfc + (0x2000 * (n)))
186 #define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
187 #define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
188 #define EIP197_PE_PSE_VERSION(n) (0x1efc + (0x2000 * (n)))
189 #define EIP197_PE_DEBUG(n) (0x1ff4 + (0x2000 * (n)))
190 #define EIP197_PE_OPTIONS(n) (0x1ff8 + (0x2000 * (n)))
191 #define EIP197_PE_VERSION(n) (0x1ffc + (0x2000 * (n)))
192 #define EIP197_MST_CTRL 0xfff4
193 #define EIP197_OPTIONS 0xfff8
194 #define EIP197_VERSION 0xfffc
197 #define EIP197_CLASSIFICATION_RAMS 0xe0000
198 #define EIP197_TRC_CTRL 0xf0800
199 #define EIP197_TRC_LASTRES 0xf0804
200 #define EIP197_TRC_REGINDEX 0xf0808
201 #define EIP197_TRC_PARAMS 0xf0820
202 #define EIP197_TRC_FREECHAIN 0xf0824
203 #define EIP197_TRC_PARAMS2 0xf0828
204 #define EIP197_TRC_ECCCTRL 0xf0830
205 #define EIP197_TRC_ECCSTAT 0xf0834
206 #define EIP197_TRC_ECCADMINSTAT 0xf0838
207 #define EIP197_TRC_ECCDATASTAT 0xf083c
208 #define EIP197_TRC_ECCDATA 0xf0840
209 #define EIP197_STRC_CONFIG 0xf43f0
210 #define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n)))
211 #define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n)))
212 #define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n)))
213 #define EIP197_FLUE_OFFSETS 0xf6808
214 #define EIP197_FLUE_ARC4_OFFSET 0xf680c
215 #define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n)))
216 #define EIP197_CS_RAM_CTRL 0xf7ff0
226 #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
227 #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)
245 #define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
250 #define EIP197_xDR_DMA_ERR BIT(0)
260 #define EIP197_N_RINGS_OFFSET 0
261 #define EIP197_N_RINGS_MASK GENMASK(3, 0)
263 #define EIP197_N_PES_MASK GENMASK(4, 0)
264 #define EIP97_N_PES_MASK GENMASK(2, 0)
266 #define EIP197_HWDATAW_MASK GENMASK(3, 0)
267 #define EIP97_HWDATAW_MASK GENMASK(2, 0)
271 #define EIP197_CFSIZE_MASK GENMASK(2, 0)
272 #define EIP97_CFSIZE_MASK GENMASK(3, 0)
276 #define EIP197_RFSIZE_MASK GENMASK(2, 0)
277 #define EIP97_RFSIZE_MASK GENMASK(3, 0)
284 #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0)
285 #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4)
289 #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
301 #define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0
311 #define RD_CACHE_3BITS 0x5
312 #define WR_CACHE_3BITS 0x3
313 #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0))
314 #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0))
315 #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
316 #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
317 #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
327 #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0)
340 #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0)
345 #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0)
354 #define EIP197_FUNCTION_ALL 0xffffffff
370 #define EIP197_STRC_CONFIG_SMALL_REC(s) (s<<0)
373 #define EIP197_FLUE_CONFIG_MAGIC 0xc7000004
384 #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0
385 #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1
386 #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2
387 #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3
388 #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4
389 #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5
390 #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6
391 #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7
392 #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe
393 #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf
398 #define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17)
399 #define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17)
400 #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
401 #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
402 #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
403 #define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20 (0x8 << 17)
404 #define CONTEXT_CONTROL_CRYPTO_ALG_SM4 (0xd << 17)
405 #define CONTEXT_CONTROL_DIGEST_INITIAL (0x0 << 21)
406 #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21)
407 #define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21)
408 #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21)
409 #define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23)
410 #define CONTEXT_CONTROL_CRYPTO_ALG_CRC32 (0x0 << 23)
411 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
412 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
413 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
414 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23)
415 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23)
416 #define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23)
417 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23)
418 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23)
419 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23)
420 #define CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7 << 23)
421 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256 (0xb << 23)
422 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224 (0xc << 23)
423 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512 (0xd << 23)
424 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384 (0xe << 23)
425 #define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305 (0xf << 23)
426 #define CONTEXT_CONTROL_INV_FR (0x5 << 24)
427 #define CONTEXT_CONTROL_INV_TR (0x6 << 24)
430 #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0)
431 #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0)
432 #define CONTEXT_CONTROL_CHACHA20_MODE_256_32 (2 << 0)
433 #define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0)
434 #define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0)
435 #define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0)
436 #define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0)
437 #define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17))
438 #define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK (12 << 0)
472 #define EIP197_TRC_PARAMS_SW_RESET BIT(0)
493 #define EIP197_RC_NULL 0x3ff
553 #define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12)
555 #define EIP197_TOKEN_STAT_LAST_HASH BIT(0)
557 #define EIP197_TOKEN_OPCODE_DIRECTION 0x0
558 #define EIP197_TOKEN_OPCODE_INSERT 0x2
560 #define EIP197_TOKEN_OPCODE_RETRIEVE 0x4
561 #define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa
562 #define EIP197_TOKEN_OPCODE_VERIFY 0xd
563 #define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe
564 #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)
570 token->stat = 0; in eip197_noop_token()
571 token->instructions = 0; in eip197_noop_token()
575 #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c
576 #define EIP197_TOKEN_INS_ORIGIN_IV0 0x14
577 #define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b
602 #define EIP197_OPTION_MAGIC_VALUE BIT(0)
604 #define EIP197_OPTION_RC_AUTO (0x2 << 3)
609 #define EIP197_TYPE_BCLA 0x0
610 #define EIP197_TYPE_EXTENDED 0x3
611 #define EIP197_CONTEXT_SMALL 0x2
612 #define EIP197_CONTEXT_SIZE_MASK 0x3
642 #define EIP197_FW_PUE_READY 0x14
643 #define EIP197_FW_FPP_READY 0x18
646 FW_IFPP = 0,
792 EIP197_TRC_CACHE = BIT(0),