26 #define SEC_QUEUE_AR_FROCE_ALLOC			0
30 #define SEC_QUEUE_AW_FROCE_ALLOC			0
35 #define SEC_ALGSUB_CLK_EN_REG				0x03b8
36 #define SEC_ALGSUB_CLK_DIS_REG				0x03bc
37 #define SEC_ALGSUB_CLK_ST_REG				0x535c
38 #define SEC_ALGSUB_RST_REQ_REG				0x0aa8
39 #define SEC_ALGSUB_RST_DREQ_REG				0x0aac
40 #define SEC_ALGSUB_RST_ST_REG				0x5a54
41 #define   SEC_ALGSUB_RST_ST_IS_RST			BIT(0)
43 #define SEC_ALGSUB_BUILD_RST_REQ_REG			0x0ab8
44 #define SEC_ALGSUB_BUILD_RST_DREQ_REG			0x0abc
45 #define SEC_ALGSUB_BUILD_RST_ST_REG			0x5a5c
46 #define   SEC_ALGSUB_BUILD_RST_ST_IS_RST		BIT(0)
48 #define SEC_SAA_BASE					0x00001000UL
52 #define   SEC_SAA_CTRL_GET_QM_EN			BIT(0)
54 #define SEC_ST_INTMSK1_REG				0x0200
55 #define SEC_ST_RINT1_REG				0x0400
56 #define SEC_ST_INTSTS1_REG				0x0600
57 #define SEC_BD_MNG_STAT_REG				0x0800
58 #define SEC_PARSING_STAT_REG				0x0804
59 #define SEC_LOAD_TIME_OUT_CNT_REG			0x0808
60 #define SEC_CORE_WORK_TIME_OUT_CNT_REG			0x080c
61 #define SEC_BACK_TIME_OUT_CNT_REG			0x0810
62 #define SEC_BD1_PARSING_RD_TIME_OUT_CNT_REG		0x0814
63 #define SEC_BD1_PARSING_WR_TIME_OUT_CNT_REG		0x0818
64 #define SEC_BD2_PARSING_RD_TIME_OUT_CNT_REG		0x081c
65 #define SEC_BD2_PARSING_WR_TIME_OUT_CNT_REG		0x0820
66 #define SEC_SAA_ACC_REG					0x083c
67 #define SEC_BD_NUM_CNT_IN_SEC_REG			0x0858
68 #define SEC_LOAD_WORK_TIME_CNT_REG			0x0860
69 #define SEC_CORE_WORK_WORK_TIME_CNT_REG			0x0864
70 #define SEC_BACK_WORK_TIME_CNT_REG			0x0868
71 #define SEC_SAA_IDLE_TIME_CNT_REG			0x086c
72 #define SEC_SAA_CLK_CNT_REG				0x0870
75 #define SEC_CLK_EN_REG					0x0000
76 #define SEC_CTRL_REG					0x0004
78 #define SEC_COMMON_CNT_CLR_CE_REG			0x0008
79 #define   SEC_COMMON_CNT_CLR_CE_CLEAR			BIT(0)
82 #define SEC_SECURE_CTRL_REG				0x000c
83 #define SEC_AXI_CACHE_CFG_REG				0x0010
84 #define SEC_AXI_QOS_CFG_REG				0x0014
85 #define SEC_IPV4_MASK_TABLE_REG				0x0020
86 #define SEC_IPV6_MASK_TABLE_X_REG(x)	(0x0024 + (x) * 4)
87 #define SEC_FSM_MAX_CNT_REG				0x0064
89 #define SEC_CTRL2_REG					0x0068
90 #define   SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_M		GENMASK(3, 0)
91 #define   SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_S		0
98 #define SEC_CNT_PRECISION_CFG_REG			0x006c
99 #define SEC_DEBUG_BD_CFG_REG				0x0070
100 #define   SEC_DEBUG_BD_CFG_WB_NORMAL			BIT(0)
103 #define SEC_Q_SIGHT_SEL					0x0074
104 #define SEC_Q_SIGHT_HIS_CLR				0x0078
105 #define SEC_Q_VMID_CFG_REG(q)		(0x0100 + (q) * 4)
106 #define SEC_Q_WEIGHT_CFG_REG(q)		(0x200 + (q) * 4)
107 #define SEC_STAT_CLR_REG				0x0a00
108 #define SEC_SAA_IDLE_CNT_CLR_REG			0x0a04
109 #define SEC_QM_CPL_Q_IDBUF_DFX_CFG_REG			0x0b00
110 #define SEC_QM_CPL_Q_IDBUF_DFX_RESULT_REG		0x0b04
111 #define SEC_QM_BD_DFX_CFG_REG				0x0b08
112 #define SEC_QM_BD_DFX_RESULT_REG			0x0b0c
113 #define SEC_QM_BDID_DFX_RESULT_REG			0x0b10
114 #define SEC_QM_BD_DFIFO_STATUS_REG			0x0b14
115 #define SEC_QM_BD_DFX_CFG2_REG				0x0b1c
116 #define SEC_QM_BD_DFX_RESULT2_REG			0x0b20
117 #define SEC_QM_BD_IDFIFO_STATUS_REG			0x0b18
118 #define SEC_QM_BD_DFIFO_STATUS2_REG			0x0b28
119 #define SEC_QM_BD_IDFIFO_STATUS2_REG			0x0b2c
121 #define SEC_HASH_IPV4_MASK				0xfff00000
122 #define SEC_MAX_SAA_NUM					0xa
123 #define SEC_SAA_ADDR_SIZE				0x1000
125 #define SEC_Q_INIT_REG					0x0
126 #define   SEC_Q_INIT_WO_STAT_CLEAR			0x2
127 #define   SEC_Q_INIT_AND_STAT_CLEAR			0x3
129 #define SEC_Q_CFG_REG					0x8
130 #define   SEC_Q_CFG_REORDER				BIT(0)
132 #define SEC_Q_PROC_NUM_CFG_REG				0x10
133 #define SEC_QUEUE_ENB_REG				0x18
135 #define SEC_Q_DEPTH_CFG_REG				0x50
136 #define   SEC_Q_DEPTH_CFG_DEPTH_M			GENMASK(11, 0)
137 #define   SEC_Q_DEPTH_CFG_DEPTH_S			0
139 #define SEC_Q_BASE_HADDR_REG				0x54
140 #define SEC_Q_BASE_LADDR_REG				0x58
141 #define SEC_Q_WR_PTR_REG				0x5c
142 #define SEC_Q_OUTORDER_BASE_HADDR_REG			0x60
143 #define SEC_Q_OUTORDER_BASE_LADDR_REG			0x64
144 #define SEC_Q_OUTORDER_RD_PTR_REG			0x68
145 #define SEC_Q_OT_TH_REG					0x6c
147 #define SEC_Q_ARUSER_CFG_REG				0x70
148 #define   SEC_Q_ARUSER_CFG_FA				BIT(0)
153 #define SEC_Q_AWUSER_CFG_REG				0x74
154 #define   SEC_Q_AWUSER_CFG_FA				BIT(0)
158 #define SEC_Q_ERR_BASE_HADDR_REG			0x7c
159 #define SEC_Q_ERR_BASE_LADDR_REG			0x80
160 #define SEC_Q_CFG_VF_NUM_REG				0x84
161 #define SEC_Q_SOFT_PROC_PTR_REG				0x88
162 #define SEC_Q_FAIL_INT_MSK_REG				0x300
163 #define SEC_Q_FLOW_INT_MKS_REG				0x304
164 #define SEC_Q_FAIL_RINT_REG				0x400
165 #define SEC_Q_FLOW_RINT_REG				0x404
166 #define SEC_Q_FAIL_INT_STATUS_REG			0x500
167 #define SEC_Q_FLOW_INT_STATUS_REG			0x504
168 #define SEC_Q_STATUS_REG				0x600
169 #define SEC_Q_RD_PTR_REG				0x604
170 #define SEC_Q_PRO_PTR_REG				0x608
171 #define SEC_Q_OUTORDER_WR_PTR_REG			0x60c
172 #define SEC_Q_OT_CNT_STATUS_REG				0x610
173 #define SEC_Q_INORDER_BD_NUM_ST_REG			0x650
174 #define SEC_Q_INORDER_GET_FLAG_ST_REG			0x654
175 #define SEC_Q_INORDER_ADD_FLAG_ST_REG			0x658
176 #define SEC_Q_INORDER_TASK_INT_NUM_LEFT_ST_REG		0x65c
177 #define SEC_Q_RD_DONE_PTR_REG				0x660
178 #define SEC_Q_CPL_Q_BD_NUM_ST_REG			0x700
179 #define SEC_Q_CPL_Q_PTR_ST_REG				0x704
180 #define SEC_Q_CPL_Q_H_ADDR_ST_REG			0x708
181 #define SEC_Q_CPL_Q_L_ADDR_ST_REG			0x70c
182 #define SEC_Q_CPL_TASK_INT_NUM_LEFT_ST_REG		0x710
183 #define SEC_Q_WRR_ID_CHECK_REG				0x714
184 #define SEC_Q_CPLQ_FULL_CHECK_REG			0x718
185 #define SEC_Q_SUCCESS_BD_CNT_REG			0x800
186 #define SEC_Q_FAIL_BD_CNT_REG				0x804
187 #define SEC_Q_GET_BD_CNT_REG				0x808
188 #define SEC_Q_IVLD_CNT_REG				0x80c
189 #define SEC_Q_BD_PROC_GET_CNT_REG			0x810
190 #define SEC_Q_BD_PROC_DONE_CNT_REG			0x814
191 #define SEC_Q_LAT_CLR_REG				0x850
192 #define SEC_Q_PKT_LAT_MAX_REG				0x854
193 #define SEC_Q_PKT_LAT_AVG_REG				0x858
194 #define SEC_Q_PKT_LAT_MIN_REG				0x85c
195 #define SEC_Q_ID_CLR_CFG_REG				0x900
196 #define SEC_Q_1ST_BD_ERR_ID_REG				0x904
197 #define SEC_Q_1ST_AUTH_FAIL_ID_REG			0x908
198 #define SEC_Q_1ST_RD_ERR_ID_REG				0x90c
199 #define SEC_Q_1ST_ECC2_ERR_ID_REG			0x910
200 #define SEC_Q_1ST_IVLD_ID_REG				0x914
201 #define SEC_Q_1ST_BD_WR_ERR_ID_REG			0x918
202 #define SEC_Q_1ST_ERR_BD_WR_ERR_ID_REG			0x91c
203 #define SEC_Q_1ST_BD_MAC_WR_ERR_ID_REG			0x920
206 #define SEC_DEBUG_BD_INFO_SOFT_ERR_CHECK_M	GENMASK(22, 0)
208 #define SEC_DEBUG_BD_INFO_HARD_ERR_CHECK_M	GENMASK(9, 0)
211 #define SEC_DEBUG_BD_INFO_GET_ID_M		GENMASK(19, 0)
218 #define SEC_OUT_BD_INFO_Q_ID_M			GENMASK(11, 0)
244 	return 0;  in sec_queue_map_io()
264 	return 0;  in sec_queue_ar_pkgattr()
276 	return 0;  in sec_queue_aw_pkgattr()
282 	u32 i = 0;  in sec_clk_en()
284 	writel_relaxed(0x7, base + SEC_ALGSUB_CLK_EN_REG);  in sec_clk_en()
287 		if ((readl_relaxed(base + SEC_ALGSUB_CLK_ST_REG) & 0x7) == 0x7)  in sec_clk_en()
288 			return 0;  in sec_clk_en()
299 	u32 i = 0;  in sec_clk_dis()
301 	writel_relaxed(0x7, base + SEC_ALGSUB_CLK_DIS_REG);  in sec_clk_dis()
304 		if ((readl_relaxed(base + SEC_ALGSUB_CLK_ST_REG) & 0x7) == 0)  in sec_clk_dis()
305 			return 0;  in sec_clk_dis()
317 	u32 i = 0;  in sec_reset_whole_module()
336 	i = 0;  in sec_reset_whole_module()
355 	return 0;  in sec_reset_whole_module()
380 		writel_relaxed(0x44cf9e, addr);  in sec_cache_config()
382 		writel_relaxed(0x4cfd9, addr);  in sec_cache_config()
453 	for (i = 0; i < 10; i++)  in sec_ipv6_hashmask()
454 		writel_relaxed(hash_mask[0],  in sec_ipv6_hashmask()
468 	return 0;  in sec_ipv4_hashmask()
512 	#define SEC_SID 0x600  in sec_streamid()
513 	#define SEC_VMID 0  in sec_streamid()
515 	writel_relaxed((SEC_VMID | ((SEC_SID & 0xffff) << 8)),  in sec_streamid()
602 	writel_relaxed((u32)~0, queue->regs + SEC_Q_FLOW_INT_MKS_REG);  in sec_queue_irq_disable()
607 	writel_relaxed(0, queue->regs + SEC_Q_FLOW_INT_MKS_REG);  in sec_queue_irq_enable()
612 	writel_relaxed((u32)~0, queue->regs + SEC_Q_FAIL_INT_MSK_REG);  in sec_queue_abn_irq_disable()
619 	writel_relaxed(0x0, queue->regs + SEC_QUEUE_ENB_REG);  in sec_queue_stop()
626 	queue->expected = 0;  in sec_queue_start()
628 	writel_relaxed(0x1, queue->regs + SEC_QUEUE_ENB_REG);  in sec_queue_start()
638 	for (i = 0; i < SEC_Q_NUM; i++)  in sec_alloc_queue()
670 	return 0;  in sec_queue_free()
742 	return 0;  in sec_queue_irq_init()
749 	return 0;  in sec_queue_irq_uninit()
760 	for (i = 0; i < SEC_MAX_DEVICES; i++) {  in sec_device_get()
882 	return 0;  in sec_queue_send()
913 	writel_relaxed(0x100, queue->regs + SEC_Q_OT_TH_REG);  in sec_queue_hw_init()
923 	u32 sec_ipv4_mask = 0;  in sec_hw_init()
939 	writel_relaxed(GENMASK(info->num_saas - 1, 0),  in sec_hw_init()
948 	sec_data_axiwr_otsd_cfg(info, 0x7);  in sec_hw_init()
949 	sec_data_axird_otsd_cfg(info, 0x7);  in sec_hw_init()
960 	writel_relaxed((u32)~0, info->regs[SEC_SAA] + SEC_FSM_MAX_CNT_REG);  in sec_hw_init()
971 	sec_set_dbg_bd_cfg(info, 0);  in sec_hw_init()
974 		for (i = 0; i < SEC_Q_NUM; i++) {  in sec_hw_init()
977 			writel_relaxed(0x3f,  in sec_hw_init()
983 	for (i = 0; i < info->num_saas; i++) {  in sec_hw_init()
985 		sec_saa_int_mask(info, i, 0);  in sec_hw_init()
988 	return 0;  in sec_hw_init()
995 	for (i = 0; i < SEC_MAX_SAA_NUM; i++) {  in sec_hw_exit()
996 		sec_saa_int_mask(info, i, (u32)~0);  in sec_hw_exit()
997 		sec_saa_getqm_en(info, i, 0);  in sec_hw_exit()
1015 	for (i = 0; i < SEC_NUM_ADDR_REGIONS; i++) {  in sec_map_io()
1033 	return 0;  in sec_map_io()
1057 	return 0;  in sec_base_init()
1091 	atomic_set(&ring_cmd->used, 0);  in sec_queue_res_cfg()
1110 	if (queue->task_irq < 0) {  in sec_queue_res_cfg()
1115 	return 0;  in sec_queue_res_cfg()
1162 	return 0;  in sec_queue_config()
1174 	int ret = 0;  in sec_id_alloc()
1179 	for (i = 0; i < SEC_MAX_DEVICES; i++)  in sec_id_alloc()
1223 					     sizeof(struct sec_hw_sgl), 64, 0);  in sec_probe()
1235 	for (i = 0; i < SEC_Q_NUM; i++) {  in sec_probe()
1260 	return 0;  in sec_probe()
1265 	for (j = i - 1; j >= 0; j--) {  in sec_probe()
1284 	for (i = 0; i < SEC_Q_NUM; i++) {  in sec_remove()
1300 	{ "HISI02C1", 0 },