Lines Matching +full:0 +full:x100008
21 #define QM_VF_AEQ_INT_SOURCE 0x0
22 #define QM_VF_AEQ_INT_MASK 0x4
23 #define QM_VF_EQ_INT_SOURCE 0x8
24 #define QM_VF_EQ_INT_MASK 0xc
26 #define QM_IRQ_VECTOR_MASK GENMASK(15, 0)
27 #define QM_IRQ_TYPE_MASK GENMASK(15, 0)
29 #define QM_ABN_IRQ_TYPE_MASK GENMASK(7, 0)
32 #define QM_MB_PING_ALL_VFS 0xffff
34 #define QM_MB_CMD_DATA_MASK GENMASK(31, 0)
38 #define QM_SQ_HOP_NUM_SHIFT 0
42 #define QM_SQ_PRIORITY_SHIFT 0
45 #define QM_QC_PASID_ENABLE 0x1
48 #define QM_SQ_TYPE_MASK GENMASK(3, 0)
49 #define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc).w11) >> 6) & 0x1)
52 #define QM_CQ_HOP_NUM_SHIFT 0
56 #define QM_CQ_PHASE_SHIFT 0
59 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
61 #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc).w11) >> 6) & 0x1)
67 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
68 #define QM_EQE_CQN_MASK GENMASK(15, 0)
70 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
72 #define QM_AEQE_TYPE_MASK 0xf
73 #define QM_AEQE_CQN_MASK GENMASK(15, 0)
74 #define QM_CQ_OVERFLOW 0
79 #define QM_XQ_DEPTH_MASK GENMASK(15, 0)
81 #define QM_DOORBELL_CMD_SQ 0
86 #define QM_DOORBELL_BASE_V1 0x340
90 #define QM_PAGE_SIZE 0x0034
91 #define QM_QP_DB_INTERVAL 0x10000
92 #define QM_DB_TIMEOUT_CFG 0x100074
93 #define QM_DB_TIMEOUT_SET 0x1fffff
95 #define QM_MEM_START_INIT 0x100040
96 #define QM_MEM_INIT_DONE 0x100044
97 #define QM_VFT_CFG_RDY 0x10006c
98 #define QM_VFT_CFG_OP_WR 0x100058
99 #define QM_VFT_CFG_TYPE 0x10005c
100 #define QM_VFT_CFG 0x100060
101 #define QM_VFT_CFG_OP_ENABLE 0x100054
102 #define QM_PM_CTRL 0x100148
105 #define QM_VFT_CFG_DATA_L 0x100064
106 #define QM_VFT_CFG_DATA_H 0x100068
119 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)
121 #define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0)
123 #define QM_ABNORMAL_INT_SOURCE 0x100000
124 #define QM_ABNORMAL_INT_MASK 0x100004
125 #define QM_ABNORMAL_INT_MASK_VALUE 0x7fff
126 #define QM_ABNORMAL_INT_STATUS 0x100008
127 #define QM_ABNORMAL_INT_SET 0x10000c
128 #define QM_ABNORMAL_INF00 0x100010
129 #define QM_FIFO_OVERFLOW_TYPE 0xc0
131 #define QM_FIFO_OVERFLOW_VF 0x3f
133 #define QM_ABNORMAL_INF01 0x100014
134 #define QM_DB_TIMEOUT_TYPE 0xc0
136 #define QM_DB_TIMEOUT_VF 0x3f
138 #define QM_ABNORMAL_INF02 0x100018
140 #define QM_RAS_CE_ENABLE 0x1000ec
141 #define QM_RAS_FE_ENABLE 0x1000f0
142 #define QM_RAS_NFE_ENABLE 0x1000f4
143 #define QM_RAS_CE_THRESHOLD 0x1000f8
145 #define QM_OOO_SHUTDOWN_SEL 0x1040f8
146 #define QM_AXI_RRESP_ERR BIT(0)
152 #define QM_PEH_VENDOR_ID 0x1000d8
153 #define ACC_VENDOR_ID_VALUE 0x5a5a
154 #define QM_PEH_DFX_INFO0 0x1000fc
155 #define QM_PEH_DFX_INFO1 0x100100
156 #define QM_PEH_DFX_MASK (BIT(0) | BIT(2))
159 #define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
160 #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
162 #define ACC_MASTER_TRANS_RETURN 0x300150
163 #define ACC_MASTER_GLOBAL_CTRL 0x300000
164 #define ACC_AM_CFG_PORT_WR_EN 0x30001c
166 #define ACC_AM_ROB_ECC_INT_STS 0x300104
171 #define QM_IFC_READY_STATUS 0x100128
172 #define QM_IFC_INT_SET_P 0x100130
173 #define QM_IFC_INT_CFG 0x100134
174 #define QM_IFC_INT_SOURCE_P 0x100138
175 #define QM_IFC_INT_SOURCE_V 0x0020
176 #define QM_IFC_INT_MASK 0x0024
177 #define QM_IFC_INT_STATUS 0x0028
178 #define QM_IFC_INT_SET_V 0x002C
179 #define QM_IFC_SEND_ALL_VFS GENMASK(6, 0)
180 #define QM_IFC_INT_SOURCE_CLR GENMASK(63, 0)
181 #define QM_IFC_INT_SOURCE_MASK BIT(0)
182 #define QM_IFC_INT_DISABLE BIT(0)
183 #define QM_IFC_INT_STATUS_MASK BIT(0)
184 #define QM_IFC_INT_SET_MASK BIT(0)
198 #define QM_CACHE_WB_START 0x204
199 #define QM_CACHE_WB_DONE 0x208
200 #define QM_FUNC_CAPS_REG 0x3100
201 #define QM_CAPBILITY_VERSION GENMASK(7, 0)
208 #define QM_PCI_COMMAND_INVALID ~0
219 #define QM_SHAPER_CIR_B_MASK GENMASK(7, 0)
230 #define QM_QOS_TICK 0x300U
231 #define QM_QOS_DIVISOR_CLK 0x1f40U
269 SQC_VFT = 0,
280 QM_PF_FLR_PREPARE = 0x01,
292 QM_TOTAL_QP_NUM_CAP = 0x0,
305 QM_CAP_VF = 0x0,
317 {QM_CAP_VF, "QM_CAP_VF ", 0x3100, 0x0, 0x0, 0x6F01},
318 {QM_AEQE_NUM, "QM_AEQE_NUM ", 0x3104, 0x800, 0x4000800, 0x4000800},
320 0x3108, 0x4000400, 0x4000400, 0x4000400},
321 {QM_EQ_IRQ, "QM_EQ_IRQ ", 0x310c, 0x10000, 0x10000, 0x10000},
322 {QM_AEQ_IRQ, "QM_AEQ_IRQ ", 0x3110, 0x0, 0x10001, 0x10001},
323 {QM_ABNORMAL_IRQ, "QM_ABNORMAL_IRQ ", 0x3114, 0x0, 0x10003, 0x10003},
324 {QM_MB_IRQ, "QM_MB_IRQ ", 0x3118, 0x0, 0x0, 0x10002},
325 {MAX_IRQ_NUM, "MAX_IRQ_NUM ", 0x311c, 0x10001, 0x40002, 0x40003},
326 {EXT_BAR_INDEX, "EXT_BAR_INDEX ", 0x3120, 0x0, 0x0, 0x14},
330 {QM_SUPPORT_DB_ISOLATION, 0x30, 0, BIT(0), 0x0, 0x0, 0x0},
331 {QM_SUPPORT_FUNC_QOS, 0x3100, 0, BIT(8), 0x0, 0x0, 0x1},
332 {QM_SUPPORT_STOP_QP, 0x3100, 0, BIT(9), 0x0, 0x0, 0x1},
333 {QM_SUPPORT_STOP_FUNC, 0x3100, 0, BIT(10), 0x0, 0x0, 0x1},
334 {QM_SUPPORT_MB_COMMAND, 0x3100, 0, BIT(11), 0x0, 0x0, 0x1},
335 {QM_SUPPORT_SVA_PREFETCH, 0x3100, 0, BIT(14), 0x0, 0x0, 0x1},
339 {QM_SUPPORT_RPM, 0x3100, 0, BIT(13), 0x0, 0x0, 0x1},
343 {QM_SUPPORT_RPM, 0x3100, 0, BIT(12), 0x0, 0x0, 0x0},
347 {QM_TOTAL_QP_NUM_CAP, 0x100158, 0, GENMASK(10, 0), 0x1000, 0x400, 0x400},
348 {QM_FUNC_MAX_QP_CAP, 0x100158, 11, GENMASK(10, 0), 0x1000, 0x400, 0x400},
349 {QM_XEQ_DEPTH_CAP, 0x3104, 0, GENMASK(31, 0), 0x800, 0x4000800, 0x4000800},
350 {QM_QP_DEPTH_CAP, 0x3108, 0, GENMASK(31, 0), 0x4000400, 0x4000400, 0x4000400},
351 {QM_EQ_IRQ_TYPE_CAP, 0x310c, 0, GENMASK(31, 0), 0x10000, 0x10000, 0x10000},
352 {QM_AEQ_IRQ_TYPE_CAP, 0x3110, 0, GENMASK(31, 0), 0x0, 0x10001, 0x10001},
353 {QM_ABN_IRQ_TYPE_CAP, 0x3114, 0, GENMASK(31, 0), 0x0, 0x10003, 0x10003},
354 {QM_PF2VF_IRQ_TYPE_CAP, 0x3118, 0, GENMASK(31, 0), 0x0, 0x0, 0x10002},
355 {QM_PF_IRQ_NUM_CAP, 0x311c, 16, GENMASK(15, 0), 0x1, 0x4, 0x4},
356 {QM_VF_IRQ_NUM_CAP, 0x311c, 0, GENMASK(15, 0), 0x1, 0x2, 0x3},
407 { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
444 {1100, 100000, 0},
517 int delay = 0; in qm_wait_reset_finish()
526 return 0; in qm_wait_reset_finish()
559 ((op) ? 0x1 << QM_MB_OP_SHIFT : 0) | in qm_mb_pre_init()
560 (0x1 << QM_MB_BUSY_SHIFT)); in qm_mb_pre_init()
564 mailbox->rsvd = 0; in qm_mb_pre_init()
567 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
574 0x1), POLL_PERIOD, POLL_TIMEOUT); in hisi_qm_wait_mb_ready()
584 unsigned long tmp0 = 0, tmp1 = 0; in qm_mb_write()
594 asm volatile("ldp %0, %1, %3\n" in qm_mb_write()
595 "stp %0, %1, %2\n" in qm_mb_write()
631 return 0; in qm_mb_nolock()
654 /* op 0: set xqc information to hardware, 1: get xqc information from hardware. */
724 u16 randata = 0; in qm_db_v2()
766 writel(0x1, qm->io_base + QM_MEM_START_INIT); in qm_dev_mem_reset()
768 val & BIT(0), POLL_PERIOD, in qm_dev_mem_reset()
777 * @is_read: Whether read from reg, 0: not support read from reg.
841 return 0; in hisi_qm_set_algs()
853 for (i = 0; i < dev_algs_size; i++) in hisi_qm_set_algs()
859 *ptr = '\0'; in hisi_qm_set_algs()
863 return 0; in hisi_qm_set_algs()
881 return 0; in qm_pm_get_sync()
884 if (ret < 0) { in qm_pm_get_sync()
889 return 0; in qm_pm_get_sync()
907 qp->qp_status.cq_head = 0; in qm_cq_head_update()
925 qp->qp_status.cq_head, 0); in qm_poll_req_cb()
944 for (i = eqe_num - 1; i >= 0; i--) { in qm_work_process()
964 u16 cqn, eqe_num = 0; in qm_get_complete_eqe_num()
968 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_get_complete_eqe_num()
985 qm->status.eq_head = 0; in qm_get_complete_eqe_num()
997 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_get_complete_eqe_num()
1117 qm->status.aeq_head = 0; in qm_aeq_thread()
1124 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); in qm_aeq_thread()
1133 qp_status->sq_tail = 0; in qm_init_qp_status()
1134 qp_status->cq_head = 0; in qm_init_qp_status()
1136 atomic_set(&qp_status->used, 0); in qm_init_qp_status()
1142 u32 page_type = 0x0; in qm_init_prefetch()
1149 page_type = 0x0; in qm_init_prefetch()
1152 page_type = 0x1; in qm_init_prefetch()
1155 page_type = 0x2; in qm_init_prefetch()
1186 for (i = 0; i < table_size; i++) { in acc_shaper_calc_cbs_s()
1199 for (i = 0; i < table_size; i++) { in acc_shaper_calc_cir_s()
1204 return 0; in acc_shaper_calc_cir_s()
1216 for (cir_u = 0; cir_u <= QM_QOS_MAX_CIR_U; cir_u++) { in qm_get_shaper_para()
1224 return 0; in qm_get_shaper_para()
1235 u64 tmp = 0; in qm_vft_data_cfg()
1237 if (number > 0) { in qm_vft_data_cfg()
1289 val & BIT(0), POLL_PERIOD, in qm_set_vft_common()
1294 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR); in qm_set_vft_common()
1303 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_set_vft_common()
1304 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_set_vft_common()
1307 val & BIT(0), POLL_PERIOD, in qm_set_vft_common()
1329 return 0; in qm_shaper_init_vft()
1351 return 0; in qm_set_sqc_cqc_vft()
1354 qm_set_vft_common(qm, i, fun_num, 0, 0); in qm_set_sqc_cqc_vft()
1364 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1); in qm_get_vft_v2()
1374 return 0; in qm_get_vft_v2()
1438 writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL); in qm_hw_error_uninit_v3()
1448 for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) { in qm_log_hw_error()
1453 dev_err(dev, "%s [error status=0x%x] found\n", in qm_log_hw_error()
1514 qm_mb_pre_init(&mailbox, QM_MB_CMD_DST, 0, fun_num, 0); in qm_get_mb_cmd()
1574 int cnt = 0; in qm_wait_vf_prepare_finish()
1575 int ret = 0; in qm_wait_vf_prepare_finish()
1580 return 0; in qm_wait_vf_prepare_finish()
1637 int cnt = 0; in qm_ping_single_vf()
1641 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, fun_num, 0); in qm_ping_single_vf()
1674 u64 val = 0; in qm_ping_all_vfs()
1675 int cnt = 0; in qm_ping_all_vfs()
1679 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, QM_MB_PING_ALL_VFS, 0); in qm_ping_all_vfs()
1696 return 0; in qm_ping_all_vfs()
1717 int cnt = 0; in qm_ping_pf()
1721 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, 0, 0); in qm_ping_pf()
1750 return hisi_qm_mb(qm, QM_MB_CMD_FLUSH_QM, 0, 0, 0); in qm_drain_qm()
1755 return hisi_qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0); in qm_stop_qp()
1764 0); in qm_set_msi()
1770 return 0; in qm_set_msi()
1777 return 0; in qm_set_msi()
1783 u32 cmd = ~0; in qm_wait_msi_finish()
1784 int cnt = 0; in qm_wait_msi_finish()
1829 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_msi_v3()
1832 return 0; in qm_set_msi_v3()
1839 ret = 0; in qm_set_msi_v3()
1886 *addr = 0; in hisi_qm_unset_hw_reset()
1907 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC); in qm_create_qp_nolock()
1908 if (qp_id < 0) { in qm_create_qp_nolock()
1917 memset(qp->cqe, 0, sizeof(struct qm_cqe) * qp->cq_depth); in qm_create_qp_nolock()
1979 struct qm_sqc sqc = {0}; in qm_sq_ctx_cfg()
1982 sqc.dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size)); in qm_sq_ctx_cfg()
1986 sqc.w8 = 0; /* rand_qc */ in qm_sq_ctx_cfg()
1988 sqc.w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type)); in qm_sq_ctx_cfg()
1998 return qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 0); in qm_sq_ctx_cfg()
2005 struct qm_cqc cqc = {0}; in qm_cq_ctx_cfg()
2008 cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, QM_QC_CQE_SIZE)); in qm_cq_ctx_cfg()
2012 cqc.w8 = 0; /* rand_qc */ in qm_cq_ctx_cfg()
2027 return qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, &cqc, qp_id, 0); in qm_cq_ctx_cfg()
2063 return 0; in qm_start_qp_nolock()
2071 * After this function, qp can receive request from user. Return 0 if
2103 for (i = 0; i < qp_used; i++) { in qp_stop_fail_cb()
2115 int ret, i = 0; in qm_wait_qp_empty()
2145 return 0; in qm_wait_qp_empty()
2160 u32 state = 0; in qm_drain_qp()
2165 return 0; in qm_drain_qp()
2182 return 0; in qm_drain_qp()
2251 * done function should clear used sqe to 0.
2272 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0); in hisi_qp_send()
2276 return 0; in hisi_qp_send()
2287 writel(0x1, qm->io_base + QM_CACHE_WB_START); in hisi_qm_cache_wb()
2289 val, val & BIT(0), POLL_PERIOD, in hisi_qm_cache_wb()
2316 for (i = 0; i < qm->qp_num; i++) in hisi_qm_set_hw_reset()
2326 u8 alg_type = 0; in hisi_qm_uacce_get_queue()
2339 return 0; in hisi_qm_uacce_get_queue()
2388 * dma_mmap_coherent() requires vm_pgoff as 0 in hisi_qm_uacce_mmap()
2392 vma->vm_pgoff = 0; in hisi_qm_uacce_mmap()
2415 u32 i = 0; in hisi_qm_uacce_stop_queue()
2443 int updated = 0; in hisi_qm_is_q_updated()
2478 if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1) in hisi_qm_uacce_ioctl()
2488 return 0; in hisi_qm_uacce_ioctl()
2502 return 0; in hisi_qm_uacce_ioctl()
2517 u32 count = 0; in qm_hw_err_isolate()
2525 return 0; in qm_hw_err_isolate()
2554 return 0; in qm_hw_err_isolate()
2599 return 0; in hisi_qm_isolate_threshold_write()
2655 if (ret < 0) in qm_alloc_uacce()
2702 return 0; in qm_alloc_uacce()
2715 return 0; in qm_frozen()
2723 return 0; in qm_frozen()
2736 int ret = 0; in qm_try_frozen_vfs()
2792 for (i = num - 1; i >= 0; i--) { in hisi_qp_memory_uninit()
2831 return 0; in hisi_qp_memory_init()
2852 qm->qp_in_used = 0; in hisi_qm_pre_init()
3001 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
3003 * (VF function number 0x2)
3021 status->eq_head = 0; in qm_init_eq_aeq_status()
3022 status->aeq_head = 0; in qm_init_eq_aeq_status()
3030 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); in qm_enable_eq_aeq_interrupts()
3031 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_enable_eq_aeq_interrupts()
3033 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK); in qm_enable_eq_aeq_interrupts()
3034 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK); in qm_enable_eq_aeq_interrupts()
3039 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK); in qm_disable_eq_aeq_interrupts()
3040 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK); in qm_disable_eq_aeq_interrupts()
3045 struct qm_eqc eqc = {0}; in qm_eq_ctx_cfg()
3053 return qm_set_and_get_xqc(qm, QM_MB_CMD_EQC, &eqc, 0, 0); in qm_eq_ctx_cfg()
3058 struct qm_aeqc aeqc = {0}; in qm_aeq_ctx_cfg()
3064 return qm_set_and_get_xqc(qm, QM_MB_CMD_AEQC, &aeqc, 0, 0); in qm_aeq_ctx_cfg()
3090 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num); in __hisi_qm_start()
3099 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0); in __hisi_qm_start()
3103 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0); in __hisi_qm_start()
3110 return 0; in __hisi_qm_start()
3122 int ret = 0; in hisi_qm_start()
3129 dev_err(dev, "qp_num should not be 0\n"); in hisi_qm_start()
3154 if (ret < 0) in qm_restart()
3158 for (i = 0; i < qm->qp_num; i++) { in qm_restart()
3162 ret = qm_start_qp_nolock(qp, 0); in qm_restart()
3163 if (ret < 0) { in qm_restart()
3174 return 0; in qm_restart()
3183 for (i = 0; i < qm->qp_num; i++) { in qm_stop_started_qp()
3204 for (i = 0; i < qm->qp_num; i++) { in qm_clear_queues()
3207 memset(qp->qdma.va, 0, qp->qdma.size); in qm_clear_queues()
3210 memset(qm->qdma.va, 0, qm->qdma.size); in qm_clear_queues()
3225 int ret = 0; in hisi_qm_stop()
3259 ret = hisi_qm_set_vft(qm, 0, 0, 0); in hisi_qm_stop()
3260 if (ret < 0) { in hisi_qm_stop()
3357 if (!qps || qp_num <= 0) in hisi_qm_free_qps()
3360 for (i = qp_num - 1; i >= 0; i--) in hisi_qm_free_qps()
3388 if (dev_node < 0) in hisi_qm_sort_devices()
3389 dev_node = 0; in hisi_qm_sort_devices()
3407 return 0; in hisi_qm_sort_devices()
3430 if (!qps || !qm_list || qp_num <= 0) in hisi_qm_alloc_qps_node()
3440 for (i = 0; i < qp_num; i++) { in hisi_qm_alloc_qps_node()
3449 ret = 0; in hisi_qm_alloc_qps_node()
3484 for (i = num_vfs; i > 0; i--) { in qm_vf_q_assign()
3491 remain_q_num = 0; in qm_vf_q_assign()
3492 } else if (remain_q_num > 0) { in qm_vf_q_assign()
3503 hisi_qm_set_vft(qm, j, 0, 0); in qm_vf_q_assign()
3509 return 0; in qm_vf_q_assign()
3518 ret = hisi_qm_set_vft(qm, i, 0, 0); in qm_clear_vft_config()
3522 qm->vfs_num = 0; in qm_clear_vft_config()
3524 return 0; in qm_clear_vft_config()
3554 return 0; in qm_func_shaper_enable()
3559 u64 cir_u = 0, cir_b = 0, cir_s = 0; in qm_get_shaper_vft_qos()
3566 val & BIT(0), POLL_PERIOD, in qm_get_shaper_vft_qos()
3569 return 0; in qm_get_shaper_vft_qos()
3571 writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR); in qm_get_shaper_vft_qos()
3575 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_get_shaper_vft_qos()
3576 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_get_shaper_vft_qos()
3579 val & BIT(0), POLL_PERIOD, in qm_get_shaper_vft_qos()
3582 return 0; in qm_get_shaper_vft_qos()
3601 return 0; in qm_get_shaper_vft_qos()
3628 int cnt = 0; in qm_vf_read_qos()
3632 qm->mb_qos = 0; in qm_vf_read_qos()
3675 ir = qm_get_shaper_vft_qos(qm, 0); in qm_algqos_read()
3700 char tbuf_bdf[QM_DBG_READ_LEN] = {0}; in qm_get_qos_value()
3701 char val_buf[QM_DBG_READ_LEN] = {0}; in qm_get_qos_value()
3711 if (ret || *val == 0 || *val > QM_QOS_MAX_VAL) { in qm_get_qos_value()
3726 return 0; in qm_get_qos_value()
3738 if (*pos != 0) in qm_algqos_write()
3739 return 0; in qm_algqos_write()
3745 if (len < 0) in qm_algqos_write()
3748 tbuf[len] = '\0'; in qm_algqos_write()
3899 qm->vfs_num = 0; in hisi_qm_sriov_disable()
3911 * Enable SR-IOV according to num_vfs, 0 means disable.
3915 if (num_vfs == 0) in hisi_qm_sriov_configure()
3983 return 0; in qm_check_req_recv()
4017 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_pf_mse()
4020 return 0; in qm_set_pf_mse()
4037 * pci_find_ext_capability cannot return 0, pos does not need to be in qm_set_vf_mse()
4048 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_vf_mse()
4052 return 0; in qm_set_vf_mse()
4062 u32 nfe_enb = 0; in qm_dev_ecc_mbit_handle()
4089 int ret = 0; in qm_vf_reset_prepare()
4119 return 0; in qm_try_stop_vfs()
4175 return 0; in qm_controller_reset_prepare()
4238 unsigned long long value = 0; in qm_reset_device()
4254 return 0; in qm_reset_device()
4278 int ret = 0; in qm_vf_reset_done()
4307 return 0; in qm_try_start_vfs()
4447 return 0; in qm_controller_reset_done()
4479 return 0; in qm_controller_reset()
4521 u32 delay = 0; in hisi_qm_reset_prepare()
4740 val == BIT(0), QM_VF_RESET_WAIT_US, in qm_wait_pf_reset_finish()
4752 ret = qm_get_mb_cmd(qm, &msg, 0); in qm_wait_pf_reset_finish()
4753 qm_clear_cmd_interrupt(qm, 0); in qm_wait_pf_reset_finish()
4854 qm_handle_cmd_msg(qm, 0); in qm_cmd_process()
4871 return 0; in hisi_qm_alg_register()
4876 return 0; in hisi_qm_alg_register()
4926 return 0; in qm_register_abnormal_irq()
4930 return 0; in qm_register_abnormal_irq()
4933 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_abnormal_irq, 0, qm->dev_name, qm); in qm_register_abnormal_irq()
4961 return 0; in qm_register_mb_cmd_irq()
4964 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_mb_cmd_irq, 0, qm->dev_name, qm); in qm_register_mb_cmd_irq()
4992 return 0; in qm_register_aeq_irq()
5024 return 0; in qm_register_eq_irq()
5027 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_eq_irq, 0, qm->dev_name, qm); in qm_register_eq_irq()
5062 return 0; in qm_irqs_register()
5084 return 0; in qm_get_qp_num()
5093 return 0; in qm_get_qp_num()
5107 return 0; in qm_get_qp_num()
5121 for (i = 0; i < size; i++) { in qm_pre_store_caps()
5131 return 0; in qm_pre_store_caps()
5160 for (i = 0; i < size; i++) { in qm_get_hw_caps()
5177 if (ret < 0) { in qm_get_pci_res()
5205 qm->db_interval = 0; in qm_get_pci_res()
5212 return 0; in qm_get_pci_res()
5230 return 0; in qm_clear_device()
5234 return 0; in qm_clear_device()
5238 return 0; in qm_clear_device()
5242 return 0; in qm_clear_device()
5246 writel(0x0, qm->io_base + ACC_MASTER_GLOBAL_CTRL); in qm_clear_device()
5261 if (ret < 0) { in hisi_qm_pci_init()
5271 if (ret < 0) in hisi_qm_pci_init()
5277 if (ret < 0) { in hisi_qm_pci_init()
5286 return 0; in hisi_qm_pci_init()
5301 for (i = 0; i < qm->qp_num; i++) in hisi_qm_init_work()
5318 return 0; in hisi_qm_init_work()
5343 for (i = 0; i < qm->qp_num; i++) { in hisi_qp_alloc_memory()
5352 return 0; in hisi_qp_alloc_memory()
5364 size_t off = 0; in hisi_qm_alloc_rsv_buf()
5370 } while (0) in hisi_qm_alloc_rsv_buf()
5386 return 0; in hisi_qm_alloc_rsv_buf()
5393 size_t off = 0; in hisi_qm_memory_init()
5402 qm->factor[0].func_qos = QM_QOS_MAX_VAL; in hisi_qm_memory_init()
5409 } while (0) in hisi_qm_memory_init()
5438 return 0; in hisi_qm_memory_init()
5487 if (ret < 0) in hisi_qm_init()
5501 return 0; in hisi_qm_init()
5695 return 0; in hisi_qm_resume()