34 #define ACRYPTO_OP_DECRYPT	0
39 #define ACRYPTO_MODE_ECB		0
44 #define ACRYPTO_TYPE_AES_128	0
50 #define PCI_VENDOR_ID_HIFN		0x13A3
51 #define PCI_DEVICE_ID_HIFN_7955		0x0020
52 #define	PCI_DEVICE_ID_HIFN_7956		0x001d
56 #define HIFN_BAR0_SIZE			0x1000
57 #define HIFN_BAR1_SIZE			0x2000
58 #define HIFN_BAR2_SIZE			0x8000
62 #define HIFN_DMA_CRA			0x0C	/* DMA Command Ring Address */
63 #define HIFN_DMA_SDRA			0x1C	/* DMA Source Data Ring Address */
64 #define HIFN_DMA_RRA			0x2C	/* DMA Result Ring Address */
65 #define HIFN_DMA_DDRA			0x3C	/* DMA Destination Data Ring Address */
66 #define HIFN_DMA_STCTL			0x40	/* DMA Status and Control */
67 #define HIFN_DMA_INTREN			0x44	/* DMA Interrupt Enable */
68 #define HIFN_DMA_CFG1			0x48	/* DMA Configuration #1 */
69 #define HIFN_DMA_CFG2			0x6C	/* DMA Configuration #2 */
70 #define HIFN_CHIP_ID			0x98	/* Chip ID */
75 #define	HIFN_0_PUDATA		0x00	/* Processing Unit Data */
76 #define	HIFN_0_PUCTRL		0x04	/* Processing Unit Control */
77 #define	HIFN_0_PUISR		0x08	/* Processing Unit Interrupt Status */
78 #define	HIFN_0_PUCNFG		0x0c	/* Processing Unit Configuration */
79 #define	HIFN_0_PUIER		0x10	/* Processing Unit Interrupt Enable */
80 #define	HIFN_0_PUSTAT		0x14	/* Processing Unit Status/Chip ID */
81 #define	HIFN_0_FIFOSTAT		0x18	/* FIFO Status */
82 #define	HIFN_0_FIFOCNFG		0x1c	/* FIFO Configuration */
83 #define	HIFN_0_SPACESIZE	0x20	/* Register space size */
86 #define	HIFN_PUCTRL_CLRSRCFIFO	0x0010	/* clear source fifo */
87 #define	HIFN_PUCTRL_STOP	0x0008	/* stop pu */
88 #define	HIFN_PUCTRL_LOCKRAM	0x0004	/* lock ram */
89 #define	HIFN_PUCTRL_DMAENA	0x0002	/* enable dma */
90 #define	HIFN_PUCTRL_RESET	0x0001	/* Reset processing unit */
93 #define	HIFN_PUISR_CMDINVAL	0x8000	/* Invalid command interrupt */
94 #define	HIFN_PUISR_DATAERR	0x4000	/* Data error interrupt */
95 #define	HIFN_PUISR_SRCFIFO	0x2000	/* Source FIFO ready interrupt */
96 #define	HIFN_PUISR_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */
97 #define	HIFN_PUISR_DSTOVER	0x0200	/* Destination overrun interrupt */
98 #define	HIFN_PUISR_SRCCMD	0x0080	/* Source command interrupt */
99 #define	HIFN_PUISR_SRCCTX	0x0040	/* Source context interrupt */
100 #define	HIFN_PUISR_SRCDATA	0x0020	/* Source data interrupt */
101 #define	HIFN_PUISR_DSTDATA	0x0010	/* Destination data interrupt */
102 #define	HIFN_PUISR_DSTRESULT	0x0004	/* Destination result interrupt */
105 #define	HIFN_PUCNFG_DRAMMASK	0xe000	/* DRAM size mask */
106 #define	HIFN_PUCNFG_DSZ_256K	0x0000	/* 256k dram */
107 #define	HIFN_PUCNFG_DSZ_512K	0x2000	/* 512k dram */
108 #define	HIFN_PUCNFG_DSZ_1M	0x4000	/* 1m dram */
109 #define	HIFN_PUCNFG_DSZ_2M	0x6000	/* 2m dram */
110 #define	HIFN_PUCNFG_DSZ_4M	0x8000	/* 4m dram */
111 #define	HIFN_PUCNFG_DSZ_8M	0xa000	/* 8m dram */
112 #define	HIFN_PUNCFG_DSZ_16M	0xc000	/* 16m dram */
113 #define	HIFN_PUCNFG_DSZ_32M	0xe000	/* 32m dram */
114 #define	HIFN_PUCNFG_DRAMREFRESH	0x1800	/* DRAM refresh rate mask */
115 #define	HIFN_PUCNFG_DRFR_512	0x0000	/* 512 divisor of ECLK */
116 #define	HIFN_PUCNFG_DRFR_256	0x0800	/* 256 divisor of ECLK */
117 #define	HIFN_PUCNFG_DRFR_128	0x1000	/* 128 divisor of ECLK */
118 #define	HIFN_PUCNFG_TCALLPHASES	0x0200	/* your guess is as good as mine... */
119 #define	HIFN_PUCNFG_TCDRVTOTEM	0x0100	/* your guess is as good as mine... */
120 #define	HIFN_PUCNFG_BIGENDIAN	0x0080	/* DMA big endian mode */
121 #define	HIFN_PUCNFG_BUS32	0x0040	/* Bus width 32bits */
122 #define	HIFN_PUCNFG_BUS16	0x0000	/* Bus width 16 bits */
123 #define	HIFN_PUCNFG_CHIPID	0x0020	/* Allow chipid from PUSTAT */
124 #define	HIFN_PUCNFG_DRAM	0x0010	/* Context RAM is DRAM */
125 #define	HIFN_PUCNFG_SRAM	0x0000	/* Context RAM is SRAM */
126 #define	HIFN_PUCNFG_COMPSING	0x0004	/* Enable single compression context */
127 #define	HIFN_PUCNFG_ENCCNFG	0x0002	/* Encryption configuration */
130 #define	HIFN_PUIER_CMDINVAL	0x8000	/* Invalid command interrupt */
131 #define	HIFN_PUIER_DATAERR	0x4000	/* Data error interrupt */
132 #define	HIFN_PUIER_SRCFIFO	0x2000	/* Source FIFO ready interrupt */
133 #define	HIFN_PUIER_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */
134 #define	HIFN_PUIER_DSTOVER	0x0200	/* Destination overrun interrupt */
135 #define	HIFN_PUIER_SRCCMD	0x0080	/* Source command interrupt */
136 #define	HIFN_PUIER_SRCCTX	0x0040	/* Source context interrupt */
137 #define	HIFN_PUIER_SRCDATA	0x0020	/* Source data interrupt */
138 #define	HIFN_PUIER_DSTDATA	0x0010	/* Destination data interrupt */
139 #define	HIFN_PUIER_DSTRESULT	0x0004	/* Destination result interrupt */
142 #define	HIFN_PUSTAT_CMDINVAL	0x8000	/* Invalid command interrupt */
143 #define	HIFN_PUSTAT_DATAERR	0x4000	/* Data error interrupt */
144 #define	HIFN_PUSTAT_SRCFIFO	0x2000	/* Source FIFO ready interrupt */
145 #define	HIFN_PUSTAT_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */
146 #define	HIFN_PUSTAT_DSTOVER	0x0200	/* Destination overrun interrupt */
147 #define	HIFN_PUSTAT_SRCCMD	0x0080	/* Source command interrupt */
148 #define	HIFN_PUSTAT_SRCCTX	0x0040	/* Source context interrupt */
149 #define	HIFN_PUSTAT_SRCDATA	0x0020	/* Source data interrupt */
150 #define	HIFN_PUSTAT_DSTDATA	0x0010	/* Destination data interrupt */
151 #define	HIFN_PUSTAT_DSTRESULT	0x0004	/* Destination result interrupt */
152 #define	HIFN_PUSTAT_CHIPREV	0x00ff	/* Chip revision mask */
153 #define	HIFN_PUSTAT_CHIPENA	0xff00	/* Chip enabled mask */
154 #define	HIFN_PUSTAT_ENA_2	0x1100	/* Level 2 enabled */
155 #define	HIFN_PUSTAT_ENA_1	0x1000	/* Level 1 enabled */
156 #define	HIFN_PUSTAT_ENA_0	0x3000	/* Level 0 enabled */
157 #define	HIFN_PUSTAT_REV_2	0x0020	/* 7751 PT6/2 */
158 #define	HIFN_PUSTAT_REV_3	0x0030	/* 7751 PT6/3 */
161 #define	HIFN_FIFOSTAT_SRC	0x7f00	/* Source FIFO available */
162 #define	HIFN_FIFOSTAT_DST	0x007f	/* Destination FIFO available */
165 #define	HIFN_FIFOCNFG_THRESHOLD	0x0400	/* must be written as 1 */
170 #define	HIFN_1_DMA_CRAR		0x0c	/* DMA Command Ring Address */
171 #define	HIFN_1_DMA_SRAR		0x1c	/* DMA Source Ring Address */
172 #define	HIFN_1_DMA_RRAR		0x2c	/* DMA Result Ring Address */
173 #define	HIFN_1_DMA_DRAR		0x3c	/* DMA Destination Ring Address */
174 #define	HIFN_1_DMA_CSR		0x40	/* DMA Status and Control */
175 #define	HIFN_1_DMA_IER		0x44	/* DMA Interrupt Enable */
176 #define	HIFN_1_DMA_CNFG		0x48	/* DMA Configuration */
177 #define	HIFN_1_PLL		0x4c	/* 795x: PLL config */
178 #define	HIFN_1_7811_RNGENA	0x60	/* 7811: rng enable */
179 #define	HIFN_1_7811_RNGCFG	0x64	/* 7811: rng config */
180 #define	HIFN_1_7811_RNGDAT	0x68	/* 7811: rng data */
181 #define	HIFN_1_7811_RNGSTS	0x6c	/* 7811: rng status */
182 #define	HIFN_1_7811_MIPSRST	0x94	/* 7811: MIPS reset */
183 #define	HIFN_1_REVID		0x98	/* Revision ID */
184 #define	HIFN_1_UNLOCK_SECRET1	0xf4
185 #define	HIFN_1_UNLOCK_SECRET2	0xfc
186 #define	HIFN_1_PUB_RESET	0x204	/* Public/RNG Reset */
187 #define	HIFN_1_PUB_BASE		0x300	/* Public Base Address */
188 #define	HIFN_1_PUB_OPLEN	0x304	/* Public Operand Length */
189 #define	HIFN_1_PUB_OP		0x308	/* Public Operand */
190 #define	HIFN_1_PUB_STATUS	0x30c	/* Public Status */
191 #define	HIFN_1_PUB_IEN		0x310	/* Public Interrupt enable */
192 #define	HIFN_1_RNG_CONFIG	0x314	/* RNG config */
193 #define	HIFN_1_RNG_DATA		0x318	/* RNG data */
194 #define	HIFN_1_PUB_MEM		0x400	/* start of Public key memory */
195 #define	HIFN_1_PUB_MEMEND	0xbff	/* end of Public key memory */
198 #define	HIFN_DMACSR_D_CTRLMASK	0xc0000000	/* Destinition Ring Control */
199 #define	HIFN_DMACSR_D_CTRL_NOP	0x00000000	/* Dest. Control: no-op */
200 #define	HIFN_DMACSR_D_CTRL_DIS	0x40000000	/* Dest. Control: disable */
201 #define	HIFN_DMACSR_D_CTRL_ENA	0x80000000	/* Dest. Control: enable */
202 #define	HIFN_DMACSR_D_ABORT	0x20000000	/* Destinition Ring PCIAbort */
203 #define	HIFN_DMACSR_D_DONE	0x10000000	/* Destinition Ring Done */
204 #define	HIFN_DMACSR_D_LAST	0x08000000	/* Destinition Ring Last */
205 #define	HIFN_DMACSR_D_WAIT	0x04000000	/* Destinition Ring Waiting */
206 #define	HIFN_DMACSR_D_OVER	0x02000000	/* Destinition Ring Overflow */
207 #define	HIFN_DMACSR_R_CTRL	0x00c00000	/* Result Ring Control */
208 #define	HIFN_DMACSR_R_CTRL_NOP	0x00000000	/* Result Control: no-op */
209 #define	HIFN_DMACSR_R_CTRL_DIS	0x00400000	/* Result Control: disable */
210 #define	HIFN_DMACSR_R_CTRL_ENA	0x00800000	/* Result Control: enable */
211 #define	HIFN_DMACSR_R_ABORT	0x00200000	/* Result Ring PCI Abort */
212 #define	HIFN_DMACSR_R_DONE	0x00100000	/* Result Ring Done */
213 #define	HIFN_DMACSR_R_LAST	0x00080000	/* Result Ring Last */
214 #define	HIFN_DMACSR_R_WAIT	0x00040000	/* Result Ring Waiting */
215 #define	HIFN_DMACSR_R_OVER	0x00020000	/* Result Ring Overflow */
216 #define	HIFN_DMACSR_S_CTRL	0x0000c000	/* Source Ring Control */
217 #define	HIFN_DMACSR_S_CTRL_NOP	0x00000000	/* Source Control: no-op */
218 #define	HIFN_DMACSR_S_CTRL_DIS	0x00004000	/* Source Control: disable */
219 #define	HIFN_DMACSR_S_CTRL_ENA	0x00008000	/* Source Control: enable */
220 #define	HIFN_DMACSR_S_ABORT	0x00002000	/* Source Ring PCI Abort */
221 #define	HIFN_DMACSR_S_DONE	0x00001000	/* Source Ring Done */
222 #define	HIFN_DMACSR_S_LAST	0x00000800	/* Source Ring Last */
223 #define	HIFN_DMACSR_S_WAIT	0x00000400	/* Source Ring Waiting */
224 #define	HIFN_DMACSR_ILLW	0x00000200	/* Illegal write (7811 only) */
225 #define	HIFN_DMACSR_ILLR	0x00000100	/* Illegal read (7811 only) */
226 #define	HIFN_DMACSR_C_CTRL	0x000000c0	/* Command Ring Control */
227 #define	HIFN_DMACSR_C_CTRL_NOP	0x00000000	/* Command Control: no-op */
228 #define	HIFN_DMACSR_C_CTRL_DIS	0x00000040	/* Command Control: disable */
229 #define	HIFN_DMACSR_C_CTRL_ENA	0x00000080	/* Command Control: enable */
230 #define	HIFN_DMACSR_C_ABORT	0x00000020	/* Command Ring PCI Abort */
231 #define	HIFN_DMACSR_C_DONE	0x00000010	/* Command Ring Done */
232 #define	HIFN_DMACSR_C_LAST	0x00000008	/* Command Ring Last */
233 #define	HIFN_DMACSR_C_WAIT	0x00000004	/* Command Ring Waiting */
234 #define	HIFN_DMACSR_PUBDONE	0x00000002	/* Public op done (7951 only) */
235 #define	HIFN_DMACSR_ENGINE	0x00000001	/* Command Ring Engine IRQ */
238 #define	HIFN_DMAIER_D_ABORT	0x20000000	/* Destination Ring PCIAbort */
239 #define	HIFN_DMAIER_D_DONE	0x10000000	/* Destination Ring Done */
240 #define	HIFN_DMAIER_D_LAST	0x08000000	/* Destination Ring Last */
241 #define	HIFN_DMAIER_D_WAIT	0x04000000	/* Destination Ring Waiting */
242 #define	HIFN_DMAIER_D_OVER	0x02000000	/* Destination Ring Overflow */
243 #define	HIFN_DMAIER_R_ABORT	0x00200000	/* Result Ring PCI Abort */
244 #define	HIFN_DMAIER_R_DONE	0x00100000	/* Result Ring Done */
245 #define	HIFN_DMAIER_R_LAST	0x00080000	/* Result Ring Last */
246 #define	HIFN_DMAIER_R_WAIT	0x00040000	/* Result Ring Waiting */
247 #define	HIFN_DMAIER_R_OVER	0x00020000	/* Result Ring Overflow */
248 #define	HIFN_DMAIER_S_ABORT	0x00002000	/* Source Ring PCI Abort */
249 #define	HIFN_DMAIER_S_DONE	0x00001000	/* Source Ring Done */
250 #define	HIFN_DMAIER_S_LAST	0x00000800	/* Source Ring Last */
251 #define	HIFN_DMAIER_S_WAIT	0x00000400	/* Source Ring Waiting */
252 #define	HIFN_DMAIER_ILLW	0x00000200	/* Illegal write (7811 only) */
253 #define	HIFN_DMAIER_ILLR	0x00000100	/* Illegal read (7811 only) */
254 #define	HIFN_DMAIER_C_ABORT	0x00000020	/* Command Ring PCI Abort */
255 #define	HIFN_DMAIER_C_DONE	0x00000010	/* Command Ring Done */
256 #define	HIFN_DMAIER_C_LAST	0x00000008	/* Command Ring Last */
257 #define	HIFN_DMAIER_C_WAIT	0x00000004	/* Command Ring Waiting */
258 #define	HIFN_DMAIER_PUBDONE	0x00000002	/* public op done (7951 only) */
259 #define	HIFN_DMAIER_ENGINE	0x00000001	/* Engine IRQ */
262 #define	HIFN_DMACNFG_BIGENDIAN	0x10000000	/* big endian mode */
263 #define	HIFN_DMACNFG_POLLFREQ	0x00ff0000	/* Poll frequency mask */
264 #define	HIFN_DMACNFG_UNLOCK	0x00000800
265 #define	HIFN_DMACNFG_POLLINVAL	0x00000700	/* Invalid Poll Scalar */
266 #define	HIFN_DMACNFG_LAST	0x00000010	/* Host control LAST bit */
267 #define	HIFN_DMACNFG_MODE	0x00000004	/* DMA mode */
268 #define	HIFN_DMACNFG_DMARESET	0x00000002	/* DMA Reset # */
269 #define	HIFN_DMACNFG_MSTRESET	0x00000001	/* Master Reset # */
272 #define HIFN_PLL_REF_CLK_HBI	0x00000000	/* HBI reference clock */
273 #define HIFN_PLL_REF_CLK_PLL	0x00000001	/* PLL reference clock */
274 #define HIFN_PLL_BP		0x00000002	/* Reference clock bypass */
275 #define HIFN_PLL_PK_CLK_HBI	0x00000000	/* PK engine HBI clock */
276 #define HIFN_PLL_PK_CLK_PLL	0x00000008	/* PK engine PLL clock */
277 #define HIFN_PLL_PE_CLK_HBI	0x00000000	/* PE engine HBI clock */
278 #define HIFN_PLL_PE_CLK_PLL	0x00000010	/* PE engine PLL clock */
279 #define HIFN_PLL_RESERVED_1	0x00000400	/* Reserved bit, must be 1 */
281 #define HIFN_PLL_ND_MULT_2	0x00000000	/* PLL clock multiplier 2 */
282 #define HIFN_PLL_ND_MULT_4	0x00000800	/* PLL clock multiplier 4 */
283 #define HIFN_PLL_ND_MULT_6	0x00001000	/* PLL clock multiplier 6 */
284 #define HIFN_PLL_ND_MULT_8	0x00001800	/* PLL clock multiplier 8 */
285 #define HIFN_PLL_ND_MULT_10	0x00002000	/* PLL clock multiplier 10 */
286 #define HIFN_PLL_ND_MULT_12	0x00002800	/* PLL clock multiplier 12 */
287 #define HIFN_PLL_IS_1_8		0x00000000	/* charge pump (mult. 1-8) */
288 #define HIFN_PLL_IS_9_12	0x00010000	/* charge pump (mult. 9-12) */
293 #define	HIFN_PUBRST_RESET	0x00000001	/* reset public/rng unit */
296 #define	HIFN_PUBBASE_ADDR	0x00003fff	/* base address */
299 #define	HIFN_PUBOPLEN_MOD_M	0x0000007f	/* modulus length mask */
300 #define	HIFN_PUBOPLEN_MOD_S	0		/* modulus length shift */
301 #define	HIFN_PUBOPLEN_EXP_M	0x0003ff80	/* exponent length mask */
303 #define	HIFN_PUBOPLEN_RED_M	0x003c0000	/* reducend length mask */
307 #define	HIFN_PUBOP_AOFFSET_M	0x0000007f	/* A offset mask */
308 #define	HIFN_PUBOP_AOFFSET_S	0		/* A offset shift */
309 #define	HIFN_PUBOP_BOFFSET_M	0x00000f80	/* B offset mask */
311 #define	HIFN_PUBOP_MOFFSET_M	0x0003f000	/* M offset mask */
313 #define	HIFN_PUBOP_OP_MASK	0x003c0000	/* Opcode: */
314 #define	HIFN_PUBOP_OP_NOP	0x00000000	/*  NOP */
315 #define	HIFN_PUBOP_OP_ADD	0x00040000	/*  ADD */
316 #define	HIFN_PUBOP_OP_ADDC	0x00080000	/*  ADD w/carry */
317 #define	HIFN_PUBOP_OP_SUB	0x000c0000	/*  SUB */
318 #define	HIFN_PUBOP_OP_SUBC	0x00100000	/*  SUB w/carry */
319 #define	HIFN_PUBOP_OP_MODADD	0x00140000	/*  Modular ADD */
320 #define	HIFN_PUBOP_OP_MODSUB	0x00180000	/*  Modular SUB */
321 #define	HIFN_PUBOP_OP_INCA	0x001c0000	/*  INC A */
322 #define	HIFN_PUBOP_OP_DECA	0x00200000	/*  DEC A */
323 #define	HIFN_PUBOP_OP_MULT	0x00240000	/*  MULT */
324 #define	HIFN_PUBOP_OP_MODMULT	0x00280000	/*  Modular MULT */
325 #define	HIFN_PUBOP_OP_MODRED	0x002c0000	/*  Modular RED */
326 #define	HIFN_PUBOP_OP_MODEXP	0x00300000	/*  Modular EXP */
329 #define	HIFN_PUBSTS_DONE	0x00000001	/* operation done */
330 #define	HIFN_PUBSTS_CARRY	0x00000002	/* carry */
333 #define	HIFN_PUBIEN_DONE	0x00000001	/* operation done interrupt */
336 #define	HIFN_RNGCFG_ENA		0x00000001	/* enable rng */
392 #define HIFN_FLAG_CMD_BUSY	(1 << 0)
440 #define	HIFN_D_LENGTH			0x0000ffff
441 #define	HIFN_D_NOINVALID		0x01000000
442 #define	HIFN_D_MASKDONEIRQ		0x02000000
443 #define	HIFN_D_DESTOVER			0x04000000
444 #define	HIFN_D_OVER			0x08000000
445 #define	HIFN_D_LAST			0x20000000
446 #define	HIFN_D_JUMP			0x40000000
447 #define	HIFN_D_VALID			0x80000000
456 #define	HIFN_BASE_CMD_COMP		0x0100	/* enable compression engine */
457 #define	HIFN_BASE_CMD_PAD		0x0200	/* enable padding engine */
458 #define	HIFN_BASE_CMD_MAC		0x0400	/* enable MAC engine */
459 #define	HIFN_BASE_CMD_CRYPT		0x0800	/* enable crypt engine */
460 #define	HIFN_BASE_CMD_DECODE		0x2000
461 #define	HIFN_BASE_CMD_SRCLEN_M		0xc000
463 #define	HIFN_BASE_CMD_DSTLEN_M		0x3000
465 #define	HIFN_BASE_CMD_LENMASK_HI	0x30000
466 #define	HIFN_BASE_CMD_LENMASK_LO	0x0ffff
478 #define	HIFN_CRYPT_CMD_ALG_MASK		0x0003		/* algorithm: */
479 #define	HIFN_CRYPT_CMD_ALG_DES		0x0000		/*   DES */
480 #define	HIFN_CRYPT_CMD_ALG_3DES		0x0001		/*   3DES */
481 #define	HIFN_CRYPT_CMD_ALG_RC4		0x0002		/*   RC4 */
482 #define	HIFN_CRYPT_CMD_ALG_AES		0x0003		/*   AES */
483 #define	HIFN_CRYPT_CMD_MODE_MASK	0x0018		/* Encrypt mode: */
484 #define	HIFN_CRYPT_CMD_MODE_ECB		0x0000		/*   ECB */
485 #define	HIFN_CRYPT_CMD_MODE_CBC		0x0008		/*   CBC */
486 #define	HIFN_CRYPT_CMD_MODE_CFB		0x0010		/*   CFB */
487 #define	HIFN_CRYPT_CMD_MODE_OFB		0x0018		/*   OFB */
488 #define	HIFN_CRYPT_CMD_CLR_CTX		0x0040		/* clear context */
489 #define	HIFN_CRYPT_CMD_KSZ_MASK		0x0600		/* AES key size: */
490 #define	HIFN_CRYPT_CMD_KSZ_128		0x0000		/*  128 bit */
491 #define	HIFN_CRYPT_CMD_KSZ_192		0x0200		/*  192 bit */
492 #define	HIFN_CRYPT_CMD_KSZ_256		0x0400		/*  256 bit */
493 #define	HIFN_CRYPT_CMD_NEW_KEY		0x0800		/* expect new key */
494 #define	HIFN_CRYPT_CMD_NEW_IV		0x1000		/* expect new iv */
495 #define	HIFN_CRYPT_CMD_SRCLEN_M		0xc000
498 #define	HIFN_MAC_CMD_ALG_MASK		0x0001
499 #define	HIFN_MAC_CMD_ALG_SHA1		0x0000
500 #define	HIFN_MAC_CMD_ALG_MD5		0x0001
501 #define	HIFN_MAC_CMD_MODE_MASK		0x000c
502 #define	HIFN_MAC_CMD_MODE_HMAC		0x0000
503 #define	HIFN_MAC_CMD_MODE_SSL_MAC	0x0004
504 #define	HIFN_MAC_CMD_MODE_HASH		0x0008
505 #define	HIFN_MAC_CMD_MODE_FULL		0x0004
506 #define	HIFN_MAC_CMD_TRUNC		0x0010
507 #define	HIFN_MAC_CMD_RESULT		0x0020
508 #define	HIFN_MAC_CMD_APPEND		0x0040
509 #define	HIFN_MAC_CMD_SRCLEN_M		0xc000
516 #define	HIFN_MAC_CMD_POS_IPSEC		0x0200
517 #define	HIFN_MAC_CMD_NEW_KEY		0x0800
519 #define	HIFN_COMP_CMD_SRCLEN_M		0xc000
521 #define	HIFN_COMP_CMD_ONE		0x0100	/* must be one */
522 #define	HIFN_COMP_CMD_CLEARHIST		0x0010	/* clear history */
523 #define	HIFN_COMP_CMD_UPDATEHIST	0x0008	/* update history */
524 #define	HIFN_COMP_CMD_LZS_STRIP0	0x0004	/* LZS: strip zero */
525 #define	HIFN_COMP_CMD_MPPC_RESTART	0x0004	/* MPPC: restart */
526 #define	HIFN_COMP_CMD_ALG_MASK		0x0001	/* compression mode: */
527 #define	HIFN_COMP_CMD_ALG_MPPC		0x0001	/*   MPPC */
528 #define	HIFN_COMP_CMD_ALG_LZS		0x0000	/*   LZS */
533 	volatile __le16		src_cnt;		/* 15:0 of source count */
534 	volatile __le16		dst_cnt;		/* 15:0 of dest count */
537 #define	HIFN_BASE_RES_DSTOVERRUN	0x0200	/* destination overrun */
538 #define	HIFN_BASE_RES_SRCLEN_M		0xc000	/* 17:16 of source count */
540 #define	HIFN_BASE_RES_DSTLEN_M		0x3000	/* 17:16 of dest count */
548 #define	HIFN_COMP_RES_LCB_M		0xff00	/* longitudinal check byte */
550 #define	HIFN_COMP_RES_RESTART		0x0004	/* MPPC: restart */
551 #define	HIFN_COMP_RES_ENDMARKER		0x0002	/* LZS: end marker seen */
552 #define	HIFN_COMP_RES_SRC_NOTZERO	0x0001	/* source expired */
557 	/* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
560 #define	HIFN_MAC_RES_MISCOMPARE		0x0002	/* compare failed */
561 #define	HIFN_MAC_RES_SRC_NOTZERO	0x0001	/* source expired */
568 #define	HIFN_CRYPT_RES_SRC_NOTZERO	0x0001	/* source expired */
571 #define	HIFN_POLL_FREQUENCY	0x1
575 #define	HIFN_POLL_SCALAR	0x0
578 #define	HIFN_MAX_SEGLEN		0xffff		/* maximum dma segment len */
579 #define	HIFN_MAX_DMALEN		0x3ffff		/* maximum dma length */
589 #define ASYNC_FLAGS_MISALIGNED	(1 << 0)
614 	return readl(dev->bar[0] + reg);  in hifn_read_0()
624 	writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);  in hifn_write_0()
637 	for (i = 10000; i > 0; --i) {  in hifn_wait_puc()
660 	hifn_write_0(dev, HIFN_0_PUIER, 0);  in hifn_stop_device()
661 	hifn_write_1(dev, HIFN_1_DMA_IER, 0);  in hifn_stop_device()
669 	 * Setting poll frequency and others to 0.  in hifn_reset_dma()
698 	for (i = 0; i < cnt; i++) {  in hifn_next_signature()
700 		v = a & 0x80080125;  in hifn_next_signature()
721 		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
722 		  0x00, 0x00, 0x00, 0x00, 0x00 }
727 		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
728 		  0x00, 0x00, 0x00, 0x00, 0x00 }
740 	if (nsec <= 0)  in hifn_rng_data_present()
743 		return 0;  in hifn_rng_data_present()
778 #define hifn_register_rng(dev)		0
789 	for (i = 100; i > 0; --i) {  in hifn_init_pubrng()
792 		if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)  in hifn_init_pubrng()
817 	return 0;  in hifn_init_pubrng()
826 	for (i = 0; i < ARRAY_SIZE(pci2id); i++) {  in hifn_enable_crypto()
847 	hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);  in hifn_enable_crypto()
850 	for (i = 0; i < 12; ++i) {  in hifn_enable_crypto()
851 		addr = hifn_next_signature(addr, offtbl[i] + 0x101);  in hifn_enable_crypto()
860 	return 0;  in hifn_enable_crypto()
869 	for (i = 0; i < HIFN_D_CMD_RSIZE; ++i)  in hifn_init_dma()
871 				offsetof(struct hifn_dma, command_bufs[i][0]));  in hifn_init_dma()
872 	for (i = 0; i < HIFN_D_RES_RSIZE; ++i)  in hifn_init_dma()
874 				offsetof(struct hifn_dma, result_bufs[i][0]));  in hifn_init_dma()
878 			offsetof(struct hifn_dma, cmdr[0]));  in hifn_init_dma()
880 			offsetof(struct hifn_dma, srcr[0]));  in hifn_init_dma()
882 			offsetof(struct hifn_dma, dstr[0]));  in hifn_init_dma()
884 			offsetof(struct hifn_dma, resr[0]));  in hifn_init_dma()
886 	dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;  in hifn_init_dma()
887 	dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;  in hifn_init_dma()
888 	dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;  in hifn_init_dma()
911 	if (strncmp(hifn_pll_ref, "ext", 3) == 0)  in hifn_init_pll()
916 	if (hifn_pll_ref[3] != '\0')  in hifn_init_pll()
967 				offsetof(struct hifn_dma, cmdr[0]));  in hifn_init_registers()
969 				offsetof(struct hifn_dma, srcr[0]));  in hifn_init_registers()
971 				offsetof(struct hifn_dma, dstr[0]));  in hifn_init_registers()
973 				offsetof(struct hifn_dma, resr[0]));  in hifn_init_registers()
976 #if 0  in hifn_init_registers()
1015 #if 0  in hifn_init_registers()
1021 	hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);  in hifn_init_registers()
1065 	cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);  in hifn_setup_crypto_command()
1070 	cry_cmd->header_skip = 0;  in hifn_setup_crypto_command()
1071 	cry_cmd->reserved = 0;  in hifn_setup_crypto_command()
1107 	mask = 0;  in hifn_setup_cmd_desc()
1126 		u16 md = 0;  in hifn_setup_cmd_desc()
1199 		dma->cmdi = 0;  in hifn_setup_cmd_desc()
1208 	return 0;  in hifn_setup_cmd_desc()
1228 			HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));  in hifn_setup_src_desc()
1233 				(last ? HIFN_D_LAST : 0));  in hifn_setup_src_desc()
1234 		idx = 0;  in hifn_setup_src_desc()
1262 		dma->resi = 0;  in hifn_setup_res_desc()
1286 			HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));  in hifn_setup_dst_desc()
1291 				(last ? HIFN_D_LAST : 0));  in hifn_setup_dst_desc()
1292 		idx = 0;  in hifn_setup_dst_desc()
1319 		hifn_setup_src_desc(dev, spage, soff, len, n - len == 0);  in hifn_setup_dma()
1325 	t = &rctx->walk.cache[0];  in hifn_setup_dma()
1331 			doff = 0;  in hifn_setup_dma()
1341 		hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0);  in hifn_setup_dma()
1350 	return 0;  in hifn_setup_dma()
1361 	w->num = 0;  in hifn_cipher_walk_init()
1362 	for (i = 0; i < num; ++i) {  in hifn_cipher_walk_init()
1371 		sg_set_page(s, page, PAGE_SIZE, 0);  in hifn_cipher_walk_init()
1382 	for (i = 0; i < w->num; ++i) {  in hifn_cipher_walk_exit()
1387 		s->length = 0;  in hifn_cipher_walk_exit()
1390 	w->num = 0;  in hifn_cipher_walk_exit()
1397 	int idx = 0;  in skcipher_add()
1429 	tidx = idx = 0;  in hifn_cipher_walk()
1430 	offset = 0;  in hifn_cipher_walk()
1449 			if (err < 0)  in hifn_cipher_walk()
1488 				if (err < 0)  in hifn_cipher_walk()
1513 	unsigned int nbytes = req->cryptlen, idx = 0;  in hifn_setup_session()
1520 	rctx->walk.flags = 0;  in hifn_setup_session()
1536 		if (err < 0)  in hifn_setup_session()
1541 	if (sg_num < 0) {  in hifn_setup_session()
1561 	return 0;  in hifn_setup_session()
1581 	dev->started = dev->active = 0;  in hifn_start_device()
1596 	return 0;  in hifn_start_device()
1604 	int idx = 0;  in skcipher_get()
1620 		offset = 0;  in skcipher_get()
1642 	if (dev->started < 0)  in hifn_complete_sa()
1646 	BUG_ON(dev->started < 0);  in hifn_complete_sa()
1655 		int idx = 0, err;  in hifn_process_ready()
1679 			if (err < 0) {  in hifn_process_ready()
1706 	while (u != 0) {  in hifn_clear_rings()
1712 			dev->reset = 0;  in hifn_clear_rings()
1718 			i = 0;  in hifn_clear_rings()
1724 	while (u != 0) {  in hifn_clear_rings()
1728 			i = 0;  in hifn_clear_rings()
1734 	while (u != 0) {  in hifn_clear_rings()
1738 			i = 0;  in hifn_clear_rings()
1744 	while (u != 0) {  in hifn_clear_rings()
1748 			i = 0;  in hifn_clear_rings()
1765 	int reset = 0;  in hifn_work()
1766 	u32 r = 0;  in hifn_work()
1769 	if (dev->active == 0) {  in hifn_work()
1772 		if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {  in hifn_work()
1776 		if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {  in hifn_work()
1780 		if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {  in hifn_work()
1784 		if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {  in hifn_work()
1811 			for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {  in hifn_work()
1823 			dev->reset = 0;  in hifn_work()
1846 	if ((dmacsr & dev->dmareg) == 0)  in hifn_interrupt()
1884 	if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {  in hifn_interrupt()
1903 	for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {  in hifn_flush()
1908 				(d->l & __cpu_to_le32(HIFN_D_VALID)) ? -ENODEV : 0);  in hifn_flush()
1941 	return 0;  in hifn_setkey()
1960 	return 0;  in hifn_des3_setkey()
2028 	int err = 0;  in hifn_process_queue()
2244 	return 0;  in hifn_init_tfm()
2271 	alg->alg.base.cra_alignmask = 0;  in hifn_alg_alloc()
2303 	for (i = 0; i < ARRAY_SIZE(hifn_alg_templates); ++i) {  in hifn_register_alg()
2309 	return 0;  in hifn_register_alg()
2326 	hifn_clear_rings(dev, 0);  in hifn_tasklet_callback()
2354 	if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||  in hifn_probe()
2374 	for (i = 0; i < 3; ++i) {  in hifn_probe()
2399 	for (i = 0; i < HIFN_D_RES_RSIZE; ++i)  in hifn_probe()
2412 		dev->irq = 0;  in hifn_probe()
2435 	return 0;  in hifn_probe()
2450 	for (i = 0; i < 3; ++i)  in hifn_probe()
2486 		for (i = 0; i < 3; ++i)  in hifn_remove()
2500 	{ 0 }
2527 	if (hifn_pll_ref[3] != '\0') {  in hifn_init()
2537 	if (err < 0) {  in hifn_init()
2546 	return 0;  in hifn_init()